Evolvable Systems Course No 2 Static and Dynamic

Evolvable Systems Course No. 2: Static and Dynamic Configurable Systems (paper by Sanchez, Sipper, Haenni, Beuchat, Stauffer, Uribe) “Politehnica” University of Timisoara Summer Semester 2007

FPGAs: What Are They ? ? Ø Large and fast integrated circuits: – Programmable: acronym from Field Programmable Gate Array – Large: 105+ logic gates – Fast: 0. 5+ GHz clock technology Ø Can be modified or configured almost at any point by the user

Configurable VS Programmable Ø Programmable computing paradigm: – General purpose processor – Instruction set (limited set of operations): instructions fetched, decoded and executed – Low cost per application – Short delivery time Ø Configurable computing paradigm: – Still a processor (logic structures) – Still a limited set of operations (logic functions) But at a much lower level!! – Configurations string directly used to configure the hardware – Longer design and delivery time – Not general purpose -> higher cost

Configurable VS Programmable (2) Ø Program -> design (algorithm) within the programmable computing paradigm Ø Configuration (configuration string) -> design/description of a configurable processor within the configurable computing paradigm Ø Configuration strings: – Static – does not change during execution Objectives: improving performance, optimizing resource utilization – Dynamic – can change during execution Objectives: adaptation to changing (dynamic) specifications, eliminate human design

Static Configurable Systems: The SPYDER Architecture Ø Reconfigurable processor development system – anagram from REconfigurable Processor Development SYstem – Static reconfiguration – Performance improving Ø Reconfigurable coprocessor that self adapts to a given application in a transparent manner Ø Application written in a high-level language (rather than an assembly program) Ø Compiler generates best-adapted hardware description

Static Configurable Systems: The SPYDER Architecture (2) Ø Fixed control unit, equivalent to a microprogrammed control unit – a sequencer – a very large memory Microprogram does not interpret a given assembly Ø It is the program to be executed Ø 8 MHz clock speed due to technology and economics Ø

Static Configurable Systems: The SPYDER Architecture (3) Meant as a SPARC coprocessor Ø VME bus interface Ø Sequencer: Xilinx 4003 Ø Program Units: Xilinx 4008 Ø

Static Configurable Systems: The SPYDER Architecture (4) Ø Performance: – 608 x 608 matrix of cells – xlife on Micro. SPARC 2 (85 MHz): future state for 6. 5 millions cells/second – SPYDER (8 MHz): future state for 115 millions cells/second – Skeletonization – Micro. SPARC 2 (85 MHz): 34. 7 seconds – SPYDER (8 MHz): 1. 17 seconds – Edge detection – SPARC Station 5 (85 MHz): 1400 ms – SPYDER (6. 25 MHz): 25 ms

Static Configurable Systems: The RENCO Architecture Ø Reconfigurable processor development system – Acronym from REconfigurable Network COmputer – Static reconfiguration – Performance improving Ø Standard network coupled with reconfigurable surface Ø User can download from the network the hardware configuration for the application to be executed

Static Configurable Systems: The RENCO Architecture (2) Ø Motorola MC 68 EN 360 processor Ø Reconfigurable area – cluster of Altera FPGAs Ø Boot EPROM, Flash RAM, DRAM

Static Configurable Systems: The RENCO Architecture (3) Ø Two pieces of software required Ø Network computer: RTEMS 1 (Real-Time Executive for Multiprocessor Systems), a preemptive multitasking operating system Ø Reconfigurable FPGA cluster: synthesizer, monitor for resources access and configuration loading, debugger, user interface, etc. Validation through design prototyping Ø

Dynamic Configurable Systems: The Fire. Fly Machine Ø Reconfigurable platform – Dynamic reconfiguration – Adaptation to changing/incomplete specifications Ø Evolvable hardware architecture – Genetic algorithms describing a population of fireflies, implemented in hardware – Based on the cellular automata model (also seen in Game of Life) made of 56 cells Ø System must evolve toward a global synchronization solution

Dynamic Configurable Systems: The Fire. Fly Machine (2)

Dynamic Configurable Systems: The Fire. Fly Machine (3) Ø Initialization phase: – the (eight) rule bits loaded with random values – carried out once per evolutionary run Ø Execution phase: – rule bits remain unchanged – several random configurations run by the system to calculate a fitness value Ø Evolutionary phase: – cell's genome (represented by its rule table) may evolve via the application of genetic operators – done in a completely local manner: only the genomes of the neighboring cells may be consulted

Dynamic Configurable Systems: The Fire. Fly Machine (4) Ø Performance gains: – Cellular programming algorithm generates 60 initial configurations/second when run on a high performance workstation – Fire. Fly 1 MHz: 13000 configurations/second – Fire. Fly 6 MHz: 6 x 13000 configurations/second Ø Synchronization task: not a real world application, used as a benchmark problem for the evolware demonstrator

Dynamic Configurable Systems: The Bio. Watch Ø Reconfigurable platform – Dynamic reconfiguration – Handle changing/incomplete specifications – Application: a digital watch capable of hierarchical self-repair Ø Part of the Embryonics project: – One dimensional artificial organism – 4 cells, each containing full genetic program – Each cell a binary decision machine

Dynamic Configurable Systems: The Bio. Watch (2) Ø Performance – not speed related: – Self-repair: partial reconstruction of a faulty organism – Faulty cells may be replaced by spare cells – Based on coordinate mechanism – Self-replication: total reconstruction of an organism – Depending on availability of spare cells only

Conclusions Ø Two kinds of reconfiguration – static and dynamic Ø Static reconfiguration mainly aimed towards improving performance Ø Dynamic reconfiguration aimed at achieving new degrees of self-repair and self-replication Ø Adaptive systems, evolutionary systems, …