Evolution in Complexity Evolution in Transistor Count Evolution

Evolution in Complexity Evolution in Transistor Count

Evolution in Speed/Performance

Intel 4004 Micro. Processor Intel Pentium (II) microprocessor

Design Abstraction Levels

Silicon in 2010 Die Area: 2. 5 x 2. 5 cm Voltage: 0. 6 V Technology: 0. 07 m

The Devices Jan M. Rabaey

The MOS Transistor

Current-Voltage Relations

Dynamic Behavior of MOS Transistor

THE INVERTERS

DIGITAL GATES Fundamental Parameters • • Functionality Reliability, Robustness Area Performance – Speed (delay) – Power Consumption – Energy

The CMOS Inverter: A First Glance

VTC of Real Inverter

Delay Definitions

CMOS Inverters VDD PMOS 1. 2 mm =2 l In Out Metal 1 Polysilicon NMOS GND

Scaling Relationships for Long Channel Devices

COMBINATIONAL LOGIC

Overview

Static CMOS

Example Gate: NAND

Transistor Sizing

4 -input NAND Gate Vdd Out GND In 1 In 2 In 3 In 4

Ratioed Logic

Pseudo-NMOS

Dynamic Logic

Example

Cascading Dynamic Gates

Domino Logic

Where Does Power Go in CMOS?

SEQUENTIAL LOGIC

Master-Slave Flip-Flop

CMOS Clocked SR- Flip. Flop

2 phase non-overlapping clocks

Pipelining

Arithmetic Building Blocks

A Generic Digital Processor

Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath (adder , multiplier, shifter, comparator, etc. ) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic. ) - Counters Interconnect - Switches - Arbiters - Bus

Bit-Sliced Design

Layout Strategies for Bit-Sliced Datapaths

Layout of Bit-sliced Datapaths

COPING WITH INTERCONNECT

Impact of Interconnect Parasitics

Using Cascaded Buffers

ISSUES IN TIMING

The Ellmore Delay

The Clock Skew Problem