ESE 566 HardwareSoftware CoDesign of Embedded Systems Fall

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ESE 566: Hardware/Software Co-Design of Embedded Systems Fall 2005 Instructor: Dr. Alex Doboli. Paper

ESE 566: Hardware/Software Co-Design of Embedded Systems Fall 2005 Instructor: Dr. Alex Doboli. Paper discussed in class: R. Ernst, J. Henkel, T. Benner, “Hardware-Software Cosynthesis of Microcontrollers”, IEEE Design & Test of Computers, Vol. 10, No, 4, December 1993, pp. 6475.

Brief description of the paper content • What is the paper discussing?

Brief description of the paper content • What is the paper discussing?

The context of the work • What kind of applications are the authors considering?

The context of the work • What kind of applications are the authors considering? • What kind of architecture are the authors considering? • What existing limitations are addressed in this work? Are these limitations still there?

The context of the work • What other alternative solutions exist to this problem?

The context of the work • What other alternative solutions exist to this problem? • How would you compare the proposed solution to the alternative solutions? • Do you think that the approach could be used for other types of applications also?

Description of the proposed solution • Summarize the solution proposed by the authors. •

Description of the proposed solution • Summarize the solution proposed by the authors. • What is the methodology? What performance constraints are the authors considering? What is the target architecture for their implementation?

Description of the proposed solution • What is the methodology? What kind of descriptions

Description of the proposed solution • What is the methodology? What kind of descriptions fit the methodology (control-driven/data-driven/mixture of data & control/memory centric)? What is the target architecture for their implementation? • What activities are part of their design solution?

Description of the proposed solution • What are the claims of this work? •

Description of the proposed solution • What are the claims of this work? • What are the limitations of the approach? Do you think that these limitations can be solved?

Related work • What similar work are the authors discussing? Does this work have

Related work • What similar work are the authors discussing? Does this work have fundamental differences or is it just a different technique? What are the advantages of this method over similar work? What are the limitations? Summarize the different approaches mentioned in the paper.

The Cosynthesis Methodology • What is partitioning? At what level of granularity is partitioning

The Cosynthesis Methodology • What is partitioning? At what level of granularity is partitioning performed? What issues must be considered? • Explain the cosynthesis methodology? Inputs; outputs; design activities. What is the granularity of the design? Why? Do you see a different way of organizing the flow? Does the methodology rely on other design tools? Do you see a limitation in this methodology?

System Modeling • How is the system modeled? What is the granularity of the

System Modeling • How is the system modeled? What is the granularity of the description (tasks/blocks/instructions/operations)? What language constructs are needed? What language constructs cannot be handled? Are these limitations important? Do you see a solutions to address these limitations?

Extended-Syntax Graph • What is an intermediate representation? Why do we need an intermediate

Extended-Syntax Graph • What is an intermediate representation? Why do we need an intermediate representation for (why not just the input specification)? • What are the characteristics of ES Graphs? What design activities are the characteristics useful for? • Is there any way you would improve ES Graphs?

Hardware/software Partitioning • How are the obtained hardware-software implementations executed? Is this correct in

Hardware/software Partitioning • How are the obtained hardware-software implementations executed? Is this correct in real-life? Is there any link between the execution model and the cosynthesis methodology? • Present the hardware-software partitioning method

Hardware/software Partitioning • Simulated Annealing algorithm • Cost function for SA. Describe the cost

Hardware/software Partitioning • Simulated Annealing algorithm • Cost function for SA. Describe the cost function. How do you validate your cost function?

Hardware/software Partitioning • Profiling: what data is collected through profiling? What can you predict

Hardware/software Partitioning • Profiling: what data is collected through profiling? What can you predict using this data (functionality, communication, performance)? What can you not predict using this data? • How is data communicated between processor and co-processor? How is communication cost evaluated? Why is communication difficult to evaluate? What elements are not considered in the current evaluation method?

Target Architecture • Detail the hardware architecture.

Target Architecture • Detail the hardware architecture.

Experiments • Experimental set-up: What experiments were performed? What was the benchmark? What was

Experiments • Experimental set-up: What experiments were performed? What was the benchmark? What was observed? Are these experiments sufficient to support the paper claims? What other design tools did the authors use? • What results were obtained? What was observed? What unexpected results have been seen?

Discussions • What are the limitations of the approach? • Summarize the work and

Discussions • What are the limitations of the approach? • Summarize the work and its merit. • Ideas for improving the work?