ESD for the Fabless Semiconductor Company Golden Rules
ESD for the Fabless Semiconductor Company Golden Rules of ESD Due Diligence for Third Party Intellectual Property By Rosario Consiglio, Impulse Semiconductor 2006
Rule #1 It is never too early to make ESD planning is part of your design flow.
Frequent ESD Management Pitfalls Insufficient time is allowed for IP vendors to correct ESD oversights and errors n Checking ESD after package design is frozen (big problem with flip-chip designs) n Putting off an ESD review until after first silicon reveals a problem n Putting off the first ESD review until just days before tape out n
Frequent ESD Problem Areas Low voltage I/O n Low voltage PLL blocks n High speed reference clock blocks n 5 volt tolerant designs on using LV CMOS n All analog IP without specifically designed I/O n More than three power supply domains n Power management circuits n
Rule #2 The Wafer Foundry will never provide all the ESD support you need.
Rule #2 Comments n n n Wafer Foundry ESD expertise is usually weighted in device design rather than ESD applications Foundry application guidelines and datasheets only cover 1 -2 basic applications (ESD NMOST, PMOST) Most Layout ESD and latchup rules are only checked manually CAD design rule checks, LVS do not include ESD checks Ask how the Foundry qualifies IP vendors
Rule # 3 The Integrated ESD level for the whole IC is always less than the sum of its third party IP parts.
Rule #3 Comments IP vendors may try, but cannot anticipate all ESD application problems with their products n Independent IP providers judge ESD performance of their individual PHY based on their respective test chip results n IP vender “A” will not guarantee their ESD circuits will protect IP from vendor “B” n
Hypothetical IC Layout Example 2 K 500 PLL Vendor E 6000 2000 AFE section Vendor A Digi tal I/O Ven dor C Digital SRAM Core Vendor D CLK SQR 4 K Digital I/O Vendor B 8000 7 K
ESD Integration Issues Due to required pin combinations, certain ESD discharge paths may be very resistive n Voltage drops on any particular path may be excessive n ESD clamps from IP vendor “A” may be incompatible with IP from vendor “B” n Insufficient isolation between IP block may result in excessive noise and Latchup n
Important IP ESD Information A test report indicating 2 KV HBM, 200 V MM, 500 V CDM is helpful but insufficient by itself n Know Pass diode resistance n Knowledge of ESD clamp dynamic resistance or ESD clamping voltage for protection elements n Know I/O cell metal layer composition, and number of squares to compute resistance n Signal buffering/Pi network configuration n
Possible IC Power Domains 9 sq 32 sq I/O clamp M=2 9 sq 3. 2 sq clamp 6. 1 sq vdd 22 sq vdd 6. 1 sq vdd 2. 2 sq vdd VDD is outer ring 28 sq vdd 3. 2 sq clamp 2. 2 sq vdd VDD 17. 5 sq vdd 28 sq vdd 25. 6 sq I/O clamp M=4 VSS is the outer ring I/O 41 sq
Modeling of Core Interconnect May be Necessary for Accurate Estimates
Rule #4 Seek out test data, ask questions.
Test Data From IP Vendors Independent Lab reports for HBM, MM, CDM results. n Transmission line pulse I/V for ESD clamps n ESD parameters extracted from TLP measurements for wafer foundry processes n Latchup current values for different I/O types over temperature n
IP Provider ESD Design Queries ESD device clamping voltages at 1. 5 amps/100 ns – is it compatible with wafer foundry ESD limits? n Noise isolation techniques – is the pass diode voltage drop less than wafer foundry technology limits? n Is the metalization wide enough for low voltage drops? n
IP Provider Design Margins Queries continued Are there antenna diodes for internal buffers, supply lines and long signal paths? n What analog signals are routed directly to I/O? n What is the input Pi network? n What foundry data used to design ESD structures? n
Foundry ESD/latchup parameters Secondary breakdown currents and voltages for ESD layouts n Worst case Oxide breakdown statistics n Resistor (poly, diffusion) current carrying capacities n Metalization current carrying capacities n Via, contact current carrrying capacities n Does the Foundry have data from SEMATECH standard ESD evaluation structures? n
SEMATECH Foundry TLP Benchmarking Structures Courtesy of Sematech
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