ES C 263 Microprocessor Programming and Interfacing BITS

ES C 263 Microprocessor Programming and Interfacing BITS Pilani Campus Pawan Sharma Lecture 18 -19 07/09 -02 -2013

Last Lecture Ø Sample programs using MOV instruction Ø INC/DEC instructions Ø Jump instruction BITS Pilani, Pilani Campus

Today’s Lecture Ø Program Control Instruction: JUMP contd… Ø Compare Instruction Ø Arithmetic instructions BITS Pilani, Pilani Campus

Copy a block of data (bytes) from one memory area to another memory area i. e. , from 42000 H , 50 data, to 44000 H BITS Pilani, Pilani Campus

X 1: MOV AX, 4000 H 10111000 00 MOV DS, AX 10001110 11011000 MOV SI, 2000 H 10111110 00 20 MOV DI, 4000 H 10111111 00 40 MOV CX, 0032 H 10111001 32 00 MOV BL, [SI] 10001010 00011100 MOV [DI], BL 1000 00011101 INC SI 01000110 INC DI 01000111 DEC CX 01001001 JNZ X 1 01110101 displacement 40

40 00000 B 8 00010 88 00001 00 00011 1 D 00002 40 00012 46 B 8 00 8 E D 8 BE 00 20 00003 8 E 00013 47 BF 00 40 00004 D 8 00014 49 B 9 32 00 00005 BE 00015 75 8 A 1 C 00006 00 00016 XX 88 1 D 00017 IP 00008 BF 00009 00 46 0000 A 40 47 0000 EH ― 00017 H 0000 B B 9 49 75 00007 20 0000 C 32 displacement F 7 H 0000 D 00 0000 E 8 A 2’s complement 0000 F 1 C representation of -9 H 9 H locations back Displacement= - 9 H

Jump Instructions Tells the computer the address to fetch the next instruction from some new location rather than from the next sequential instruction. Unconditional Jump and Conditional Jump instructions Ø Unconditional jump Instructions: Ø Intra-segment jump (Near or Short) Ø Inter-segment jump (Far) BITS Pilani, Pilani Campus

Near and Far jumps are further divided into Direct or Indirect Short jumps are always Direct - Direct : Destination address specified as a part of the instruction - Indirect: Destination address specified in a register or memory location BITS Pilani, Pilani Campus

Unconditional jump Intra segment Jump Short jump (8 bit Disp always a Direct Jump) Intersegment jump Far Jump (Both CS and IP are Changed) Near jump Direct Jump(16 bit Disp in the instruction added to IP) Indirect jump (16 bit Disp thru Reg or Memory replaces IP) Direct jump (32 bit CS and IP Values in the instruction) Indirect Jump (CS & IP values from memory) BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Direct Intra-segment jump Ø Jump anywhere in the current code segment Ø Adds the displacement contained in the instruction to the current contents of IP. Ø Signed displacement Jump forward or backward. BITS Pilani, Pilani Campus

Short jump : IP IP+d 8 (EBH) - Displacement 8 –bits +127 to -128 locations. Near Jump: IP IP+d 16 (E 9 H) - Displacement 16 bits +32, 767 to – 32, 768 locations. BITS Pilani, Pilani Campus

Backward Jump: How assembler tackles it? 0000 H 0002 H 0003 H 0004 H 0006 H back: add al, 03 h nop jmp back nop - 6 is the displacement : back FAH BITS Pilani, Pilani Campus

Forward Jump: How assembler tackles it? 0000 0003 0004 0005 THERE: JMP THERE NOP MOV AX, 0000 H Displacement = 03 H Alternative: JMP SHORT THERE BITS Pilani, Pilani Campus

Intra-segment Indirect Always of kind Near Ex: Register indirect JMP BX IP Reg 16 (IP value replaced) Ex: Indirect Memory Addressing JMP WORD PTR [BX] IP Mem 16 (IP value replaced) BITS Pilani, Pilani Campus

Intersegment Jump (FAR) Direct: Usage JMP FAR PTR START Assembled as JMP Offset Base Absolute branch IP Offset CS Base BITS Pilani, Pilani Campus

INTERSEGMENT INDIRECT Only possible through Memory Addressing Ex: JMP DWORD PTR [BX] BITS Pilani, Pilani Campus

Conditional Jump Instructions Always of kind SHORT JC/JNC Carry JZ/JNZ Zero JP/JNP Parity JS/JNS Sign JO/JNO Overflow BITS Pilani, Pilani Campus

Conditional Jump Instructions Magnitude Comparison Unsigned numbers: JA/JNBE JAE/JNB/JNC JB/JC/JNAE JBE/JNA Signed numbers: JG/JNLE JGE/JNL JL/JNGE JLE/JNG BITS Pilani, Pilani Campus

Finally…………. . JCXZ : jump if the CX register is zero. Does not look at the zero flag when it decides whether to jump or not. q Of type short BITS Pilani, Pilani Campus

Compare Instruction ØCompare instruction is a subtraction that changes only the flag bits. ØNeither source nor destination is changed. ØSource can be an immediate number, register, memory location ØDestination can be a register or memory location ØComparison done by subtracting source from destination CMP Destination, Source CMP CL, [BX] CMP AX, 2000 H CMP [DI], CH BITS Pilani, Pilani Campus

CMP CX, BX CX = BX CF-0 ZF-1 CX < BX CF-1 ZF-0 CX > BX CF-0 ZF-0 BITS Pilani, Pilani Campus

Conditional JUMP instructions BITS Pilani, Pilani Campus

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ADD Destination, Source (Source) + (Destination) Ø Source may be an immediate no. /register/ a memory location specified by any on of the 24 addressing modes Ø Destination may be a register / memory location specified by any on of the 24 addressing methods Ø Both source and destination in an instruction cannot be memory locations Ø Source and Destination must be of same size Ø All Flags Affected BITS Pilani, Pilani Campus

MOV CL, 73 H MOV BL, 4 FH ADD CL, BL Result in CL = C 2 H 11000010 b (194 d if unsigned -62 d if signed) CF = 0, PF = 0, AF = 1, ZF = 0, SF = 1, OF = 1 BITS Pilani, Pilani Campus

Write a Program to add an array of bytes stored in memory starting at 40000 H and store the result in 41000 H. Number of elements in the array = 50 d BITS Pilani, Pilani Campus

MOV BX, 0000 H MOV AX, 4000 H MOV DS, AX MOV SI, 0000 H MOV CL, 32 H MOV AH, 00 H X 2: MOV AL, [SI] ADD BX, AX INC SI DEC CL JNZ X 2 MOV [1000 H], BX BITS Pilani, Pilani Campus

ADC DESTINATION, SOURCE (SOURCE) + ( DESTINATION) + CF ( DESTINATION) § Useful for multi-byte addition of data Ø ADD AL, 74 H: Add immediate no. 74 H to contents of AL. Result is in AL. Ø ADC CL, BL : Add contents of BL with carry status to contents of CL. Result is in CL. BITS Pilani, Pilani Campus

SUB DESTINATION, SOURCE (Destination) – (Source) (Destination) SBB DESTINATION, SOURCE (Destination) - (Source) – (CF) (Destination) BITS Pilani, Pilani Campus

SUB CL, BH Unsigned numbers: CL=10011100 BH=00110111 Result=01100101 Signed numbers: CL=00101110 BH=01001010 Result=11100100 CL=10100001 BH=01001100 Result=0101 CF, AF, SF, ZF=0 OF, PF=1 AF, ZF=0, PF=1, CF=1, SF=1, OF=0 CF, ZF=0 AF, PF=1 SF=0 OF=1 BITS Pilani, Pilani Campus

Assembler Directives Data declarations DB, DW, DD DATA 1 DB 45 H, 35 H, 74 H DATA 2 DW 2000 H, 37 H, 2222 H ORG 3000 H -- Originate. Allows to set the location counter to a desired value at any point in a program. BITS Pilani, Pilani Campus

DATA 1 DATA 2 DATA 3 DB DB DB ORG DATA 4 ORG DATA 5 0010 H DB 0018 H DB 25 10001001 b 12 H ‘ 2591’ ? This is how data is initialized in the data segment 0000 19 H 0010 32 H 0001 89 H 0011 35 H 0002 12 H 0012 39 H 0013 31 H 0018 00 H BITS Pilani, Pilani Campus

MESSAGE 2 DB '1234567’ MESSAGE 3 DW 6667 H data 1 db db 1, 2, 3 45 H 'a‘ 11110000 b data 2 dw dw dd 12, 13 2345 H 300 H BITS Pilani, Pilani Campus

How it looks like in memory 31 32 33 34 35 36 37 67 00 0 D 00 45 23 00 03 00 DB 6 DUP(FFH) 31 32 33 34 35 36 37 67 00 0 D 00 45 23 00 03 00 66 01 02 03 45 61 F 0 0 C 00 ; fill 6 bytes with FFH 66 01 02 03 45 61 F 0 0 C 00 FF FF FF BITS Pilani, Pilani Campus