ENG 2410 Digital Design Week 3 Cont Combinational
ENG 2410 Digital Design: Week #3 “Cont. . Combinational Logic Circuits” S. Areibi School of Engineering University of Guelph
Week #3 Topics ¡ NAND, NOR Universal Gates l ¡ XOR Gates, XNOR Gates l ¡ ¡ ¡ ¡ ¡ AND-OR to NAND Implementations Odd/Even Parity Logic Families Electrical Characteristics 2 Multiple Level Circuits High Impedance Outputs Combinational Circuits Analysis versus Design Hierarchy CAD Tools Design Procedure
Resources Chapter #2, Mano Sections l l 2. 6 2. 7 2. 8 2. 9 Multi-Level Circuit Optimization Other Gate Types Exclusive-OR Operator and Gates High Impedance Outputs Chapter #3, Mano Sections l l l 3. 1 Design Concepts and Automation 3. 2 The Design Space 3. 3 Design Procedure
Universal Gates
NAND Gates Very common for discrete logic 5
NAND is Universal ¡ ¡ Fact: Fact Any digital circuit can be designed and realized using only AND, OR, NOT gates If we can prove that NAND gate can emulate AND, OR, NOT then we prove that it is Universal 6
NAND is Universal De. Morgan’s Theorem: Theorem Inverting the inputs of an OR gate produces a NAND gate Tie two inputs 7
NOR Gates ¡ ¡ NOT OR Also common X Y Z 0 0 1 0 1 1 0 0 8
NOR Gate is also Universal Prove that a NOR gate is Universal by showing it can perform the functionality of (a) NOT gate, (b) OR gate, (c) AND gate X Y Z 0 0 1 0 1 1 0 0 9
Conversion to all-NAND
NAND and NOR Implementations ¡ Digital circuits are frequently constructed with only NAND and NOR implementations: l Both are universal gates l they are easier to fabricate using (CMOS Technology) ¡ Because of their use, rules have been developed that allow us to convert Boolean functions using AND, OR and NOT into the equivalent NAND and NOR logic diagrams. 11
Recall Inverting the inputs of an OR gate produces a NAND gate NOT OR NAND Gate Identity 17 X. Y = X + Y 12
Conversion to all-NAND Circuits The general procedure for converting a multi-level ANDOR diagram into an all-NAND diagram is as follows: 1. 2. 3. Convert all AND gates to NAND gates with ANDNOT graphic symbols Convert all OR gates to NAND gates with NOT-OR graphic symbols Check all the bubbles in the diagram ¡ Every bubble that is not compensated by another along the same line will require the insertion of an inverter or complement the input literal 13
Sum of Products with NAND l Convert all AND gates to NAND gates with AND-NOT graphic symbols l Convert all OR gates to NAND gates with NOT-OR graphic symbols l Check all the bubbles in the diagram ¡ Every bubble that is not compensated by another along the same line will require the insertion of an inverter or complement the input literal Easy to think of bubbles as canceling 14
AND-OR Circuit Easy to Convert 15
Exclusive OR Gate
Exclusive-OR Function ¡ Exclusive-OR (XOR) performs the following function l x y = xy’ + x’y This function is equal to one only if either x or y is equal to one but not both. ¡ Another name for the XOR is: ¡ l Odd FUNCTION!! FUNCTION 17
Exclusive OR ¡ Symbol is ¡ l Plus in a circle XOR Implementations 18
Multi Input XOR 19
XNOR Function Description Logic Symbol Output Y is FALSE if input A OR input B are TRUE Exclusively, else it is TRUE. A XNOR Y B The complement of an XOR function is an XNOR (even function) Truth Table Equivalent Expression Boolean Expression Y= A B 20
Buffers
Buffer No inversion ¡ No change, except in power or voltage ¡ Used to enable driving more inputs ¡ 22
Tri-State
Tri-State Output w/ 3 states: H, L, and Hi-Z l l l High impedance Behaves like no output connection if in Hi-Z state Allows connecting multiple outputs How is this implemented in CMOS Technolgoy? 24
Recall CMOS Inverter Pull-up Network A Y 0 1 1 0 0 0 1 1 Pull-down Network 25
CMOS Tri-State Inverter OE IN OUT X Z 1 1 0 0 0 1 0 ON Z ON NO PATH TO VDD and VSS A PATH EXISTS TO BOTH VDD AND VSS 26
Multiplexed with Hi-Z Normal operation is blue area Smoke 28
Electrical Characteristics
Electrical Characteristics ¡ ¡ Fan in – max number of inputs to a gate Fan out – how many standard loads it can drive (load usually 1) Noise margin – how much electrical noise it can tolerate Power dissipation – how much power chip needs l l TTL high Some CMOS low (but look at heat sink on a Pentium) 30
Binary Signaling (Noise Margin) ¡ Zero volts l ¡ FALSE or 0 5 volts l TRUE or 1 Noise 31
Propagation Delay Max of high-to-low and low-to-high ¡ Maximum and typical given ¡ 32
Analysis
Combinational Circuits ¡ ¡ A combinational logic circuit has: l A set of m Boolean inputs, l A set of n Boolean outputs, and l The output depends only on the current input values l No Feedback, no cycles A block diagram: Combinatorial Logic Circuit m Boolean Inputs n Boolean Outputs 34
Sequential Circuits A sequential circuit consists of combinational circuits to which storage elements are connected to form a feedback path. Storage elements store binary information. Outputs of a sequential circuit are a function of the inputs and the internal state of the storage elements. 35
Analysis vs. Design ¡ Design of a circuit starts with specification and ends up with a logic diagram. ¡ Analysis for a combinational circuit consists of determining the function that the circuit implements with: v v v o A set of Boolean functions or A truth table, together with a possible explanation of the operation of the circuit. We can perform the analysis by manually finding the Boolean equations or truth table. The first step in the analysis is to make sure that the given circuit is combinational and not sequential (i. e. no feedback or storage elements). 36
Derivation of Boolean Func. Or Truth Table Label gate outputs of input variables 1. l Label outputs of gates fed by previously labeled gates 2. l 3. Determine Boolean functions or values Determine Boolean function or values Repeat 2 until done 37
Let’s do this Example 38
Cont. . Analysis Example 39
Derivation of Truth Table ¡ ¡ Make table with 2 n rows, where n is number of inputs Label some gate outputs Put those labels and the final outputs on columns of truth table Work your way across 40
Derivation of Truth Table A B C D T 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 0 T 2 T 3 T 4 F 1 F 2 41
Design
Design Procedure 1. 2. 3. 4. 5. 6. Specification l Write a specification for the circuit if one is not already available Formulation l Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification Optimization l Use K-Maps to simplify Boolean Expression. Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters Technology Mapping: Map the logic diagram or netlist to the implementation technology selected (FPGA, PCB) Verification: Verify the correctness of the final design HOW TO DEAL WITH A LARGE DESIGN? 43
Design Hierarchy ¡ Just similar to large software development: § ¡ Divide and Conquer § ¡ To design a large chip we need hierarchy To create and also to understand Block is equivalent to object 44
Example – 4 -bit Comparator ¡ Specifications: • • o Input: 2 vectors A(3: 0) and B(3: 0) Output: One bit, E, which is 1 if A and B are bitwise equal, 0 otherwise Straight forward implementation? ? • 256 entries in the Truth Table!!! • To design another comparator with operands having 5 bits you will Need to start the design from scratch and have 1024 entries … 45
Formulation ¡ Since the circuit has eight inputs, use of truth table formulation is impractical! l We need to create a truth table with 256 entries!! In order for A[3: 0] and B[3: 0] to be equal, the bit values in each of the respective positions, 3 down-to 0, of A and B must be equal. ¡ Use intuition to immediately develop a multiple level circuit. How? ¡ 46
Design: Decomposition ¡ ¡ Use Hierarchical Design: Decompose the problem into: l Four 1 -bit comparison circuits (i. e. , One Module/bit) l An additional circuit that combines the four comparison circuit outputs to obtain E (i. e. , Final Module for E) 47
Design for MX module Define the output of the circuit to be: • `0’ if both inputs are similar and • `1’ if they are different? ¡ Logic function is ¡ Can implement as Ai Bi Ei 0 0 1 1 1 0 48
4 -bit Comparison? ? ? E 49
Design of ME module Final E is 1 only if all intermediate values are 0 Design for MX module ¡ So ¡ ¡ And a design is Ai Bi Ei 0 0 1 1 1 0 50
Overall Design 51
Alternative Design for MX module Define the output of the circuit to be: • `1’ if both inputs are similar and • `0’ if they are different? Ai Bi Ei 0 0 1 0 1 0 0 1 1 1 ¡ Logic function is ¡ Can implement as 2 AND Gates and OR Gate ¡ How to design the ME Module in this case? Ei = A’i B’i + Ai Bi 52
XOR Postulates and Theorems ¡ ¡ ¡ Exclusive NOR (XNOR) can be generated by taking the complement of an XOR operation l (x y)’ = xy + x’y’ The following identities apply to XOR (IMP!) l x 0 = x l x 1 = x’ l x x = 0 l x x’ = 1 l x y’ = x’ y = (x y)’ XOR is also commutative and associative 54
XOR = Odd Function ¡ ¡ The XOR operation with three or more variables can be converted into an ordinary Boolean function by replacing the with its equivalent Boolean expression l A B C = (AB’ + A’B)C’ + (AB + A’B’)C l AB’C’ + A’BC’ + ABC + A’B’C l ∑(1, 2, 4, 7) This function is equal to 1 only if one variable is equal to 1 or if all three variables are equal to 1. l This implies that an odd number of variables must be one. This is defined as an odd function 55
Error Detecting Codes « Parity One bit added to a group of bits to make the total number of ‘ 1’s (including the parity bit) even or odd 4 -bit Example 7 -bit Example ● Even 1 0 1 1 1 0 0 0 1 ● Odd 0 0 1 1 1 0 0 0 1 « Good for checking single-bit errors 56
Parity Generation and Checking ¡ XOR functions are very useful in systems requiring errordetection and correction codes. l A circuit that generates a parity bit is called a parity generator. l The circuit that checks the parity is called a parity checker. 57
Parity Generator ¡ Design even parity generator for 3 -bit signal l l ¡ Perhaps make truth table and K-Map Draw with XOR, then sum-of-products w/ NAND gates How do you design a detector? 58
Parity Bit Implementation X Y P Z 59
Example ¡ ¡ ¡ 9 -input odd function (parity for byte) Basically checks for even parity! Block for schematic is box with labels Without hierarchy how would you start your design? 60
Design Broken Into Modules Use 3 -input odd functions 61
Use NAND to Implement XOR ¡ In case there’s no XOR, for example 62
Components in Design ¡ RHS shows what must be designed 63
Design Hierarchy 64
Design Example (continued) z 3. Optimization a. 2 -level using K-maps W = A + BC + BD C 1 1 0 1 3 4 5 7 1 X X 12 13 8 9 1 B 14 1 4 5 10 1 Z = D X 13 8 9 1 1 0 4 5 7 6 4 1 10 3 1 X 13 1 X C 2 8 B 14 11 w 1 A X X 3 12 6 15 1 1 X 7 X 12 0 X 2 D C x 3 1 X A X 11 0 D X = BC + BD + B C D Y = CD + C D X X 1 1 6 15 1 C 2 1 X A y X 15 X 9 11 D 14 X 10 B X A 1 12 1 7 X 13 1 8 1 5 X 2 6 X 15 X 9 11 D B 14 X 10 65
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