EMT 362 Microelectronic Fabrication Thin Gate Oxide Growth

EMT 362: Microelectronic Fabrication Thin Gate Oxide – Growth & Reliability Ramzan Mat Ayub School of Microelectronic Engineering

Lecture Objectives • Understand the importance and requirement of thin gate oxide • Able to describe the tecnique to grow high quality thin oxides • Understand the nature of Mode-A, B &C of breakdown failure • Able to calculate the oxide strength, τBD and QBD School of Microelectronic Engineering

Gate Oxide L GATE Gate Oxide n+ ID P-well School of Microelectronic Engineering n+

Gate Oxide Requirements • Possible to grow thin oxide precisely and uniformly across the wafer • Adequate reliability characteristics under operating conditions in terms of strength (Breakdown Voltage), Reliability of operation over specified time (τBD, QBD) and resistance to hot-carrier degradation) School of Microelectronic Engineering

Desired Gate Oxide Characteristics • The thickness closely match the specification in MOSFET design • Uniform across the wafer, from wafer to wafer, run to run. • Small interface charge • High dielectric strength • Long lifetime under normal operating conditions • High resistance to hot-carrier damage School of Microelectronic Engineering

Technology of Thin Oxide Growth 1. Oxidation furnace Vertical furnace is more favourable compared to horizontal. 3 reasons • Wafer/wafer holders make no contact with oxidation tube during loading, growth and unloading (fewer particles generated). • Lighter boat material can be used, as a result, better heat and gas distributions (result in better oxide uniformity). • Precise control of wafer to wafer spacing. School of Microelectronic Engineering

Technology of Thin Oxide Growth 2. Control of Growth Rates • Slow growth rates required to reproducibly grow thin oxides with precise thickness. • Grow in dry O 2 at atmospheric pressure at lower temperatures (800 -900 C). • Growth at reduced total pressure, or reduced O 2 partial pressure School of Microelectronic Engineering

Technology of Thin Oxide Growth Typical Thin Gate Oxide Process 1. Carried out in vertical furnace 2. Prior to oxide growth; 1. Grow and strip sacrificial oxide (to remove defect in silicon layer) 2. Cleaning procedure (normally generic of RCA cleaning) 3. Loaded by robotic wafer handling at specific insertion rates ~ 15 cm 4. per minute for 150 mm wafer, 10 cm per minute for 200 mm wafer. 5. Furnace temperature ~ 650 – 700 C. 4. Furnace temperature is ramped up to the growth temperature. During 5. temperature ramp up, N 2 or Ar is purged to prevent unwanted growth. 5. Temperature stabilization around 5 min before O 2 is released. School of Microelectronic Engineering

Technology of Thin Oxide Growth Typical Gate Oxide Process 6. Dry oxidation at atmospheric pressure at temperature ~ 800 -900 C. 7. Some companies use dry/wet/dry to control thermal budget. Othe 8. use HCl, TCA , DCE as chlorine source. 7. Wafers subjected to Post Oxidation Annealing (POA) in N 2 at + ~100 C. 8. The purpose is to minimize the interface trap density by neutralizing 9. the dangling bond of Si with H atoms. This will improve the τBD and QBD. 8. Furnace temperature is ramped down, and wafer is unloaded at certain 9. rate. School of Microelectronic Engineering

Gate Oxide Characterizations 1. Gate oxide Strength a) Breakdown voltage, then calculate the breakdown electric field. 2. Gate Oxide Reliability a) τBD – time to breakdown b) QBD – charge to breakdown School of Microelectronic Engineering

Gate Oxide Strength Definition – The maximum electric field strength that can be applied to the oxide before it breaks down. Unit MV/cm. Test procedure – Ramped Voltage Test using MOS capacitor School of Microelectronic Engineering

T 1 V GATE Gate Oxide substrate t Ig T 2 • Ramp voltage between T 1 and T 2, measure current • Take the voltage at the voltage drop as the breakdown voltage (V BD) • Calculate the oxide strength by VBD / oxide thickness School of Microelectronic Engineering VBD V

Example Thin oxide of 500 A is stressed under voltage ramp test until it breaks at 8 V. Calculate the oxide strength. Oxide strength = Breakdown voltage / oxide thickness = 8 V / 500 e-8 cm = 1. 6 e 6 V/cm = 1. 6 MV / cm School of Microelectronic Engineering

Mode of Breakdown Failure A histogram is usually used to plot the results of the ramped-voltage tests (oxide strength) of a group of oxide samples (normally up to 1000 capacitor tested to characterized certain oxidation process recipe) Breakdown Frequency Mode-B (2 -6 MV/cm) Mode-C (8 -12 MV/cm) Mode-A (<1 MV/cm) 5 Breakdown Field, MV/cm School of Microelectronic Engineering 10

Mode-A • Fail instantly upon the application of a small gate bias. • Its believed that this oxide may experienced a gross defect such as pinholes and may already be shorted before the application of low strength field. School of Microelectronic Engineering

Mode-B • Fail at electric field of intermediate strength (2 -6 MV/cm) • Contain weak spots that do not produce instant shorting, but may give rise to early failures of ICs under normal operating conditions. • Majority of oxide breakdown failure in sub-micron CMOS fall under this category. Mostly due to the defects exist in the oxide. • Defects include; • Sodium contamination – originated from W furnace filamen, chemicals • Metal contamination – from substrate, other processes • Surface roughness at Si-Si. O 2 interface from etching or cleaning procedures – promote localize weak spot • Non-uniformity of oxide growth • Crystalline defect – defect originated during crystal growth School of Microelectronic Engineering

Mode-C • Can withstand the highest electric fields (8 -12 MV/cm) • Failure mechanism always referred as intrinsic failure. • Generally assumed as defect-free oxide. • Several models proposed to explain the intrinsic breakdown • Holes generation and trapping model. Electrons are injected into the conduction band of oxide by FN tunneling. In the oxide, these electrons are accelerated towards the gate, and generate electron-hole pair in the oxide. These generated holes are trapped at the localized areas and in return trap positive oxide charge. This will increase the positive charge at certain point in the oxide, causing the tunneling current density to increase there up to critical point where the breakdown occurs. • Wolters Electron Lattice-Damage Model School of Microelectronic Engineering

Gate Oxide Reliability Gate oxide strength is not directly relevant to the normal device operation, since what is really needed is how long the thin oxide will survive at lower field strength. The measurement of oxide performance at lower electric field is called Time-Dependent Dielectric Breakdown (TDDB). • • • Time to Breakdown under Constant-Voltage Stressing (τBD) Time to Breakdown under Constant-Current Stressing (τBD) Charge to Breakdown (QBD) School of Microelectronic Engineering

Time to Breakdown under Constant-Voltage Stressing Electric field in the oxide is held constant (voltage is held constant) during the stress test. The length of time, τBD elapsed until breakdown occurs is then measured. School of Microelectronic Engineering

Time to Breakdown under Constant-Current Stressing Current is injected into the oxide by Fowler- Nordheim tunneling, and this value Iinj is held constant. Voltage and time are recorded until breakdown occurs. School of Microelectronic Engineering

Charge to Breakdown In a constant current test; QBD = Jinj. τBD In a constant voltage test; School of Microelectronic Engineering

Emperical Model to Estimate Oxide Reliability Applicable to Mode-B and Mode-C Failures 1. QBD for intrinsic oxide is approximately constant for small FN tunneling current. 2. Qp (hole charge to breakdown) also constant. Qp = JgατBD Where at 300 C School of Microelectronic Engineering sec G=350 MV/cm

Example Calculate the time-to-breakdown, τBD at 300 K of 8 nm defect free gate oxide, use in CMOS technology with Vcc 5. 0 V. τBD (300 K)= 1 e-11 (sec) exp 350 e 6. Tox / Vox = 1 e-11. exp 350 e 6. 8 e-7 / 5. 0 = 2 e 13 sec School of Microelectronic Engineering

Example Calculate the minimum thickness of a defect free oxide that could be used in a MOSFET that is to operate at 5. 5 V for 10 years at 150 C (425 K) w/out suffering oxide breakdown. Given G(425 K)= 283 MV/cm and Τ 0 (425 K)=0. 75 e-11 sec. τBD for 10 years ~ 3 e 8 sec tox min = 88 Å School of Microelectronic Engineering