EMERGING FINEPITCH BUMP BONDING TECHNIQUES LCDWG 4 Vertex

EMERGING FINE-PITCH BUMP BONDING TECHNIQUES LCD-WG 4 Vertex detector technology meeting 3 -September-2010 SAMI VAEHAENEN – CERN PH-ESE 1

Outline • Introduction • Solder bump evolution • Elements & trends • Flip chip bonding • Introduction • Chip-to-wafer-bonding • Cu pillar structures • SLID soldering • Electroless deposition technology • Lift-off bumping technology • Carbon nano fiber interconnections • Wafer thinning and thin wafer handling • Summary 2

Introduction • This presentation aims at giving an introduction of present day or near-future fine-pitch flip chip structures. • Evolution of 3 D integration processes using through silicon vias (TSV) has had a major impact on the scale-down of solder bump structures and pitches in the commercial electronics. • In the future more silicon-to-silicon flip chip assembly processes (not only Si-to. PCB) are needed for stacking chips on top of each other. • This has launched the needs for very fine-pitch bumping processed. • Economical pressure is forcing the industry to find low-cost flip chip solutions. 3

Flip Chip in Pixel Detectors • Pixel detector consists of a sensor chip and readout chip which are connected with flip chip bumps (picture below). • Because each pixel is visible in the radiation image, a high bump bonding yield is required to avoid visible defects. • Solder bumps have been typically used as connecting the chips electrically and mechanically together. 4

Elements in Solder Alloys • Elements and their masses used in typical solder joints (atomic weights): • Ni 58. 7, Cu 63. 5, In 114. 8, Sn 118. 7, Pb 207. 2 • Solder bump volumes are typically small in pixel detectors (d = 30 µm) and the areacoverage is relatively small (5% - 40%) • Solder joints have relative low mass despite using heavy elements. • Restriction of hazardous substances (Ro. Hs) directive is limiting the use of lead in interconnections: • Concentration of lead in an alloy should be less than 1000 PPM (< 0. 1%) • Exemptions for flip chip solder joints • Flip chip joints in pixel detectors are not affected by Ro. Hs directives, but less solder bumping processes are available with lead alloys. • Tin-lead solder has been replaced mainly by pure tin or Sn. Ag. Cu (SAC) or Sn. Ag alloys. • Pure tin is known to be problematic for tendency of creating tin whiskers. • Lead used to be a good whisker inhibitor. • Risk of whiskers can be reduced by limiting the tin volume and forming it into intermetallics (IMC) or by using Ni UBM with certain characteristics. • Lead free solder alloys have usually higher melting temperatures than eut. Sn. Pb alloy.

Wafer Bumping – Bump Sizes and Pitches • Techniques available: Electroplating = EP Stencil Printing = SP Solder ball placement = SBB ENIG = Electroless Ni/Au. Standard FC bump • EP FC fine-pitch bump • ENIG + SP • ENIG + SBB FC µ-bump • EP • C 4 NP Cu pillar bump • EP SLID • EP Evaporation = EV In bump • EV & lift-off

Wafer Bumping – Bump Sizes and Pitches • Two curves are drawn on this slide describing the trends of: • Estimated mass vs. interconnect technology • Estimated price of individual flip chip assembly (chip-to-chip) vs. interconnect technology 200 $ Mass Price per individual flip chip placement 100 $ (personal estimate) 10 $ 1$

Wafer Bumping – Bump Sizes and Pitches • Two curves are drawn on this slide describing the trends of: • Estimated mass vs. interconnect technology • Estimated price of individual flip chip assembly vs. interconnect technology 200 $ 10 $ 1$ Mass Low-resolution, high volume region. Industry’s major playground Price per individual flip chip placement

Wafer Bumping – Bump Sizes and Pitches • Two curves are drawn on this slide describing the trends of: • Estimated mass vs. interconnect technology • Estimated price of individual flip chip assembly vs. interconnect technology 200 $ 10 $ 1$ Mass Price per individual flip chip placement HEP pixel area. This area is gaining a lot of attention within industry

Wafer Bumping – Bump Sizes and Pitches • Two curves are drawn on this slide describing the trends of: • Estimated mass vs. interconnect technology • Estimated price of individual flip chip assembly vs. interconnect technology 200 $ 10 $ 1$ Mass Price per individual flip chip placement Advanced interconnections: • Flip chip assembly will be expensive on chiplevel.

Wafer Bumping – Bump Sizes and Pitches • Area of focus in this presentation: Cu pillars, SLID structures and other advanced interconnect technologies. • Near future technologies for sub 40 µm pitches Mass Price per individual flip chip placement Region of interest in this presentation: Technologies for 20 µm pitch

Cu Pillar Flip Chip (1/2) • Copper pillar joints have become very popular in fine-pitch bump bonding. • Structure example: • • Cu pillar (length ≈ 10 µm) and solder cap (3 – 5 µm) Solder won’t wet the sidewalls of Cu pillars if the solder volume is small enough. • Soldering can be done on: 1. Standard solderable UBM (picture 1) 2. Symmetrical Cu pillar structure (picture 2) or only Cu UBM (SLID structure) • Cu pillar structures suits better for finer pitches than traditional solder bump Sensor chip processes. • Larger solder volume limits the minimum pitch (picture 3) 1 2 3 12

Cu Pillar Flip Chip (2/2) • Pillar bump structures could be favored if the rather large stand-off height and low solder volume (mass) are required. • The only technology in this presentation which enables high stand-off heights without using solder bumps. • Main disadvantage using Cu pillar structures is that rework may be or troublesome after long baking cycles. • Low solder volume might turn completely into high melting point inter-metallic compounds. Cu pillar Solder / soldering interface Cu pillar Courtesy of Amkor 13

Solid-Liquid-Inter-Diffusion (SLID) Soldering • • In SLID tin, indium or other metals with low melting point (MP) are capped on high MP pads, because: 1. Creation of intermetallic compounds (IMC) with the pad metal. 2. High planarity requirements of metal-metal bonding (e. g. , Cu-Cu) are compensated. Solid-Liquid-Inter-Diffusion (SLID) soldering, AKA Transient-Liquid-Phase (TLP) soldering is preferred in chip stacking because high thermal budget. • Thin layer of solder turns completely into IMC ultra thin metallic joints! • After the first reflow the MP increases significantly and becomes thermally very stable. • Cu-Sn-Cu structure is the most commonly used, and with an optimized process Sn transforms to Cu 3 Sn in some minutes. Step 4: 1 Beginning: 2: 3: • After Cross-hatched All Sn long has been heating, • Thick Sn reacts the with Cu 6 Sn 5 transformed Cuphase pads to IMC’s. ductile Cu and creates and • consumes Cu 3 Sn < 5 Cu 3 Sn is µm taking the of Sn. Snover expands over the– at • IMC’s. aggressively. Cu 6 Sn 5 Bondingand at 270 grows whole Cu 6 Sn 5 phase and • 300 the Cu 3 Sn expense C. area phase of forms grows the inand big a thin Cu 6 Sn 5 on at Cu Cu. joint. scallops. interfaces.

Indium / Solder (Lift-Off) Bumping • This technology has been used since the 80’s for fine-pitch focal plane arrays (FPA) IR sensors • Lift-off technique does not include any etching steps after solder deposition and therefore fine bump sizes can be reached (picture). • Steps (picture): 1. Wafer 2. Deposition of photoresist layer 3. Reverse patterning + solder/metal evaporation 4. Photoresist stripping • In lift-off technology, the resolution of the lithography, and photoresist and evaporated metal alloy thickness are the restricting factors. • Deposition of only thin layers possible (<< 10 µm) • Very fine bumps with ultra-fine pitches can be deposited, but the process is troublesome and time Remark: Bumping process based consuming expensive. on indium lift-off technology (AMS) was used in some of ATLAS pixel detectors.

FLIP CHIP BONDING PICTURE: VTT 16

Introduction to Flip Chip Bonding • High-accuracy flip chip bonders are able to perform with ± 1. 5 µm precision. • Existed already for more than 10 years and it is seems to be sufficient for majority of applications • Precision of the state-of-the-art flip chip systems is better than 0. 5 µm • High number of I/O’s on large chips require (besides clean environment): • High thermocompression force • Good placement accuracy • Chip to substrate leveling capabilities • Good thermal stability • These requirements cause the rugged nature of the state-of-the-art flip chip equipment and the bonding processes are slow. • FC bonders become significantly faster at 10 µm placement precision • Because the need is arising for flip chip assemble chips with microbumps also for consumer electronics, the flip chip equipment manufacturers are wrestling with technical issues to increase throughput without compromising the accuracy. • The cost of fine-pitch flip chip assembly is still expensive • The detector assemblies are done on die level nowadays. • Chip-to-wafer (C 2 W) assembly technology is the most potential wafer-level technology which could be used for pixel detectors.

Common Flip Chip Bonding Techniques • Typically three flip chip bonding techniques are used: 1. Solder-to-solder tack bonding + assembly reflow. 2. Reflow bonding (e. g. , solder bonded against solderable metal pads), which is the most common method in the industry. 3. Indium-indium thermocompression bonding. • Bonding at room temperature possible 1 * Self-alignment! * Readout chip Sensor chip Tack bonding by VTT 50 µm pitch 2 Self-alignment! 3 18

C 2 W Bonding – Advanced Flip Chip • C 2 W bonding is done on a flip chip bonder, which has a large chuck (200 - 300 mm). • C 2 W bonding is more flexible than Wafer-to-Wafer (W 2 W) bonding and doesn’t suffer from yield issues. • Technology benefits • C 2 W reduces manual handling of assemblies. • Increase in the throughput – the whole wafer has to be assembled at the time. • Sensors can be bonded against known good dies (KGD) – economically efficient. • Chips with different sizes can be bonded – flexibility! • C 2 W bonding is currently being used in industry, but it hasn’t been used much in assembly of pixel detectors. • C 2 W can be considered as an intermediate step towards W 2 W bonding. Edgeless sensor chips or ROC’s with TSV’s needed - large guard ring structures or wire bonding pads consume wafer real estate. 19

C 2 W Bonding (cont’d) • Similar solder bump structures can be used as in chip-to-chip assembly, except that the wafer-level assembly and interconnections have to withstand larger thermal budget. • No degradation in soldering properties is tolerated during the long assembly cycle SLID soldering preferred – especially in multilayer assemblies! • Common assembly cycle: a) Tack-bonding (pick & place) of individual chips + mass reflow for the device wafer in reducing ambient. b) Collective bonding can be done in wafer bonder after tack bonding with a cover wafer (slow processes such as hybrid-metal bonding). • C 2 W bonding is favored when large and expensive dies are used (such as pixel chips). If two side processed chips are used, multilayer chip stacking is possible

C 2 W Bonding Using Build-Up Wafers • Readout wafers are diced and the good known dies are picked up and redistributed on a carrier wafer on an adhesive layer. • Wafer with unique stepping can be made – prototyping possibility. • After assembly, the wafer is diced, and the glue will be dissolved. Alternatively, a planarizing spin-on polymer layer will be processed on assemblies and the carrier wafer is ground away to release the assemblies. • Technology benefits • One can populate wafers with KGD to get fully electrically functioning wafers • There are no restrictions for sensor die size (large guard rings acceptable) KGD’s are pick & placed on an adhesive layer Sensor chips are assembled on ROC’s 21

FLIP CHIP R&D PICTURE: VTT 22

Electroless Under Bump Metallization (UBM) • Maskless and high volume capable technology low-cost • The most worrying issue in the given interconnect examples has been the etching of the seed layer. • Solved by electroless deposition of Ni/Au or Ni/Pd/Au UBM’s on one side of the parts. • Strength of the UBM pads is depended on the size of passivation openings to Al on the wafers. Mechanical contact only on Al – not to passivation. • Potential limits with small passivation openings to Al • Requires deposition tests Electroless process flow sketch Electroless UBM’s have been processed with 30 µm pitch test structures on CERN test wafers. 23

Carbon Nano Fiber (CNF) Interconnections • CERN has started a small project with Smoltek (Gothenburg, Sweden) to develop fine-pitch solid CNF interconnection technique for pixel chips. • Goal is set at growing 5 µm – 10 µm long fibers on chips and joining them together. • Electrical contacts will be tested with/without metal contacts. • CNF would yield ultra-low mass interconnections. • Technology has prospects to be ultra-fine pitch capable. • First CNF forests have been deposited on CERN test vehicle chips. • Development plan has been made to improve the patterning resolution and to develop suitable flip chip processes. Passivation Side profile of CNF forest 4 µm long fibers grown in a passivation opening on CERN test vehicle chip

Ultra-Fine Pitch Structures • Ultra-fine pitch bump bonding has been applied to IR FPA panels for military applications already since the 80’s. • This indium based bump bonding technology can be said to be the forerunner in the field of ultra-fine pitch bump bonding technology. • In pictures below the hollow microtubes (right) can be assembled on planarized indium (left) at the wafer passivation level (very advanced). • Interesting and hardcore technology, but the price of the bump bonding is inversely proportional to the pitch Source: SET technical bulletin 2000 x 2000 pixels with 7. 5 µm pitch. Indium has been planarized in the passivation openings. 3 µm sized hollow microtubes on 10 µm pitch with CEA LETI’s “tip in buried box 2” technique (application IR-FPA).

WAFER THINNING PICTURE: VTT 26

Wafer Thinning • Wafer thinning technology has made a giant leap during 5 last years. • Thanks to development of temporary carrier wafers technologies for thinning and thin wafer handling, reported wafer thicknesses have dived to sub 10 µm scale. • Wafers can be basically thinned down to any thickness, but the problems arise when the wafers are handled and moved from process to another. • Thin wafers break down very easily without a proper carrier wafer technology and wafer breakages become expensive (both for foundry and customer). • One cannot give a generic figure for wafer thicknesses, because it depends on the wafer manufacturing and thinning technology available. • Typically wafers are thinned in Through Silicon Via (TSV) processes to 50 µm – 100 µm thicknesses. TOK Wafer thinned with TOK Zeronewton technology

Thin Wafer Handling – Temporary Bonding Process

Thin Wafer Handling - Debond

Wafer Thinning Worries • Problems arise when the thinned wafer is removed from the carrier. • Asymmetric stresses will warp the wafers/chips after they are released. • Unless stresses are balanced the bow on a chip between corners and centre can be significant and cause alignment issues in flip chip bonding • Even 50 µm warpage is possible for 50 µm thick chip • Stresses can be balanced by optimizing film stresses on both sides of the wafer. • Thin wafers are more difficult to dice than thick ones • More chipping on backside. • Thin chips are fragile and chipping worsens further the die strength B. DANG - IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008 Chip thickness 75 um

SUMMARY PICTURE: VTT 31

Important to Know Before Choosing the Technology • Stand-off height requirement • Is there cross-talk between sensor and readout chip if the stand-off height is low. • Tests are underway to find this out. • Planarity requirements in fine-pitch bump bonding • Controlled sensor wafer manufacturing process is very important in future. • Over 100 µm bow has been recorded on 200 µm thick (125 mm) sensor wafers which are manufactured with asymmetric process. • The lower the flip chip joint is, the more planar the wafers should be. • Planarity can be controlled by thin films having either compressive or tensile stresses. • How thin one wants to go? • Thinning tests should be done on real process wafers to specify the window. • Frequent wafer breakages at the lower end of the thinning window might become very expensive.

Summary • Flip chip structures are becoming finer • More Si-on-Si packaging in 3 D integration processes. • Cu pillar bumps and SLID structures are the most likely flip chip structures when moving in the 20 - 30 µm pitch window. • Planarity of wafers will become important once the stand-off height decreases. • Stress compensation might be needed! • Flip chip of fine-pitch chips is expensive. Equipment manufacturers are looking for solutions for high accuracy and throughput. • At the moment, C 2 W assembly technique seems to be the most probable wafer-level assembly technique to be used for pixel detectors. 33

THANK YOU FOR YOUR ATTENTION! PICTURE: VTT 34

BACKUP SLIDES PICTURE: VTT 35

Electroplating Cartoon – Cu Pillars • Cu pillar bumping process using electroplating. • Pure tin or some low-melting point alloy used commonly used. 1. Wafer (zoom into pixel pad) 2. Sputtering of adhesion/barrier & seed layer for electroplating 3. Photolithography 4. Plating of under bump metal (Cu) 5. Plating of tin 6. Photoresist removal 7. Etching of seed layer (wet or dry) 8. Etching of adhesion/barrier layer 9. Solder reflow * Medipix 2 bumps by VTT * Etching of the seed layer (Cu usually) in a controlled way is the hardest step in very fine pitch bumping process by electroplating. Wet processes are commonly used, but there is undercut issue below the bump feet which 36 weakens the strength of the structure.