EMCAware System Design A focus on Integrated Circuits

EMC-Aware System Design - A focus on Integrated Circuits Etienne SICARD Professor etienne. sicard@insa-toulouse. fr www. ic-emc. org INSA TOULOUSE - FRANCE

TOULOUSE, FRANCE Founded in -120 B. C Airbus A 380 Cassoulet Best place to study in France (2015 ranking) (heavy responsibility) Rugby

CONTENTS • General context • Integrated Circuits • Electromagnetic Compatibility • Design Guidelines

1 GENERAL TRENDS DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

MARKET GROWTH Share of system sales 2020 vs 2015 VISION 2020 • Increasing Smartphones disposable income, • PC Expanding Tablets urban population, • TV Growing internet Game consoles Servers Availability of strong -10% distribution network 5 Internet of Things Medical penetration and • Automotive Electronic Market Growth 0 10% 20% Growth

MOBILE BUSINESS https: //www. gsmaintelligence. com/ 4 G 3 G 2 G http: //www. ericsson. com/ericsson-mobility-report

INTERNET OF THINGS • Growth in 2016 was stalling (+5% smarthones) • Consumer demand was sluggish (tablets, laptops). • Demand for Internet of Things (Io. T) wasn't growing fast enough to offset declines • Price, security and ease-of-use remain barriers to the adoption of new Io. T devices and services.

ADAS TOWARDS AUTOMATIC DRIVE • 2020 : Injury-free driving • 2030: Accident-free driving ? • 2040: Autonomous driving?

2 TECHNOLOGY TRENDS DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

SCALE DOWN BENEFITS • Smaller • Faster • Less power 65 nm consumption • 28 nm Cheaper (if you fabricate millions) • 14 nm Room for other devices Processors Power Memory -50% Security Sensors 65 nm 28 nm -80% 14 nm

MOBILE COMMUNICATIONS Technology Complexity 130 nm 90 nm 100 M 250 M 45 nm 500 M 28 nm 14 nm 5 nm 2 G 7 G 150 G Packaging Mobile generation Embedded blocks 3 G 2004 2007 Core+ DSP Core DSPs 1 Mb Mem 10 Mb Mem 2010 Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors 5 G 4 G+ 4 G 3 G+ 2013 Quad Core Quad DSP 3 D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors 2016 2020 ?

GOING ATOMIC SCALE • 14 -nm Xeon by Intel ™ • IBM, Global. Foundries, Samsung, SUNY first 7 -nm testchip 2017 • Qualcomm™ Snapdragon X 50 Si lattice: 0. 23 nm

GOING 3 D - MEMORIES Stacked process layers • 8, 16, 32 layers of active devices • 1 tera-bit/cm 2 achieved 5 years ahead from roadmaps

3 D IC TECHNOLOGY High Bandwidth Memory (HBM) Hybrid Memory Cube (HMC) http: //www. eej ournal. com/arti cle/20170102 hbm-hmc/ 14 September 21

GOING 3 D – Package on Package MEM to So. C (TMV) Upper MEM PCB Bottom So. C E. Sicard, EMC performance analysis of a Processor/Memory System using PCB and Package-On -Package, EMC Compo 2015 Edinburgh So. C to PCB MEM to PCB (TMV)

GOING 3 D – Stacked Dies Processor die THERE IS PLENTY OF SPACE ON THE TOP • 3 D technology uses stacked dies, through-silicon-vias • Enables 10 -20 Gb/s/pin at 1. 0 V • Possible 3 rd die Thinned memory die 10 µm Multicore 350 µm thickness Samsung 3 D (Galaxy 6) vs Po. P (Galaxy 5) : Upper die Bottom die Package leadframe (GND) 30% faster 20% less power Less heat http: //www. youtube. com/watch? v=Rw 9 fpsig. Cfk Through Silicon Via (TSV) Direct bond interconnect (DBI)

3 ELECTROMAGNETIC COMPATIBILITY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

ONE ACRONYM – TWO PROBLEMS • SUSCEPTIBILITY TO INTERFERENCE Carbon airplane • EMISSION OF PARASITIC NOISE Personal Devices Equipment interferences Boards Radar Components Hardware fault Software failure Function Loss Safety systems

SUPPLY VOLTAGE SCALE DOWN • Less noise margin (<100 m. V in 7 -nm) 10 -nm technology Supply (V) 5. 0 3. 3 0. 7 V inside, 1. 2 V outside I/O supply 2. 5 Core supply 1. 8 1. 2 1. 0 0. 35µ 0. 18µ 130 n 90 n 65 n 45 n 32 n Technology node 20 n 14 n 10 n 7 n

HIGHER FREQUENCIES 2, 3, 4, 5 G mobile frequencies 4 G 800 Today 1 GHz 5 G 700 Tomorrow 2 -4 G 1800 2 -3 G 900 5 G 3300 3 G 1900 4 G 2600 2 GHz 3 GHz 5 G 42 500 5 G 26 250 5 G 4400 10 GHz 20 GHz 30 GHz 40 GHz

MORE I/O NOISE I/O Technology • Multi-Giga-Bit link between processors & memories : video, object recogn. , 3 D capture • Generation 4 x and 5 on the market • Generation 6 under development DDR 4 x: 230 ps, 0. 25 V swing Data Rate per pin (Gb/s) 100 Gb/s Graphics trends GDDR 6 GDDR 5 Low power trends GDDR 4 10 Gb/s GDDR 3 GDDR 2 LP 2 DDR 2 LP 4 LP 3 DDR 4 DDR 3 LP 4 x DDR 4 x LP 5 DDR trends 1 Gb/s 2010 2012 2014 2016 2018 2020

WIDE RANGE OF OPERATING VOLTAGES Technology • Nano-CMOS operates below 1 V, noise margin around 50 m. V • Close to medium voltage (12, 24, 48 V) and high voltage (98, 240, 300, 400, 850 V) functions • ADC with 16 -24 bit resolution work at 10 -100 µV resolution

4 DESIGN GUIDELINES DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

MOTIVATION • Use tools, guidelines and trainings in EMC of Integrated circuits, for improved EMC before fabrication Tools DESIGN Architectural Design Guidelines Training Design Entry Design Architect EMC Simulations Compliance ? FABRICATION NO GO GO EMC compliant

DESIGN GUIDELINES - SUPPLY • Place supply pairs close to noisy blocks Current density simulation Layout view Memory PLL Digital core VDD / VSS 25

DESIGN GUIDELINES - IOS • Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs 9 I/O ports 26

DESIGN GUIDELINES – CANCEL FIELDS Radiated field • Reduce current loops that provoke magnetic field Added contributions EM wave current Lead Die Lead Reduced contributions Reduce d field 27 currents

DESIGN GUIDELINES – REDUCE SWITCHING NOISE 28 • Reduction of clock buffer’s drive • Reduce drive, limit slew rate, • Spread of the switching • Adapt impedance, • 20 d. B noise reduction • Add local decoupling • 20 d. B noise reduction J-P. Leca “Microcontrollers Electromagnetic Interferences Modeling and Reduction”, Ph. D report, Univ of Nice, France, 2012

DESIGN GUIDELINES – ISOLATE AND DECOUPLE • On-chip decoupling • Resistive supply path • Substrate isolation • Separate supply • Separation between Immunity level (d. Bm) Decoupli ng capacitan ce incompatible blocks substrat e isolatio n Substrat e isolation No rules to reduce susceptibility Separate supply 29 Work done at Eseo France Frequency

DESIGN GUIDELINES - SHIELDING • Graphene in stacked dies • 10 -15 d. B coupling reduction • Thin magnetic-nonmagnetic multi-layered structure • Trench-via array and multi-layered conductor structures (5 G, 28 -39 GHz) http: //prc. gatech. edu/hg/item/585164 K. Kim, “Graphene-based EMI Shielding for Vertical Noise Coupling Reduction in 3 D Mixed-Signal System”, 2012

CONCLUSION DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

CONCLUSION • The electronic market growth should be driven by 5 G mobile, automatic drive, Internet of Things, etc. • The trends towards nano. CMOS have been illustrated • EMC concerns in terms of noise margin, higher frequencies and IO bandwidth • Design guidelines for improved EMC have been introduced www. ic-emc. org

Thank you for your attention Special thanks to Prof. Norocel CODREANU, CETTI DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING