EMBEDDED SYSTEMS www maheshelectronics wordpress com UNIT 1

EMBEDDED SYSTEMS www. maheshelectronics. wordpress. com

UNIT – 1 1. 2. 3. 4. 5. 6. 7. 8. PART-A Embedded Systems – Introduction (Definition, Applications and Classification) Features and architecture considerations(ROM, RAM, TIMERS…) RISC Vs. CISC Von-Neumann & Harvard Architecture Memory mapped I/O and Isolated I/O Little-Endian and Big-Endian PART-B Low Power RISC- MSP 430 : Introduction & Variants of MSP 430 family MSP 430 F 2013 - Block diagram & features Memory map of MSP 430 –CPU architecture & registers Addressing modes of MSP 430 Instruction formats & Instruction Timings of MSP 430 Instruction set of MSP 430 Sample Embedded system on MSP 430 www. maheshelectronics. wordpress. com

INTRODUCTION TO EMBEDDED SYSTEMS • Definition : An embedded system is an electronic/electro-mechanical system designed to perform a specific function and is combination of both hardware and firmware (software). The program instructions written for embedded systems are referred to as firmware, and are stored in Read-Only-Memory or Flash memory. www. maheshelectronics. wordpress. com

INTRODUCTION TO EMBEDDED SYSTEMS Purpose of Embedded System • Data Collection/Storage/Representation • Data communication • Data processing • Monitoring • Control • Application specific user interface www. maheshelectronics. wordpress. com

INTRODUCTION TO EMBEDDED SYSTEMS • • • • Applications of Embedded Systems Household appliances Automotive industry Home automation & security systems Telecom Computer peripherals Computer networking systems Healthcare Banking & Retail Card Readers Measurements & Instrumentation Missiles and Satellites Robotics Motor control systems Entertainment systems Signal & Image processing www. maheshelectronics. wordpress. com

INTRODUCTION TO EMBEDDED SYSTEMS • Classification of Embedded Systems: • The classification of embedded system is based on following criteria's: • On generation • On complexity & performance www. maheshelectronics. wordpress. com

INTRODUCTION TO EMBEDDED SYSTEMS • Classification based on generation • 1. First generation(1 G): 8 -bit μp and 4 -bit μc. • 2. Second generation(2 G): 16 -bit μp and 8 -bit μc. • 3. Third generation(3 G): 32 -bit μp & 16 -bit μc. • 4. Fourth generation(4 G): 64 -bit μp & 32 -bit μc. www. maheshelectronics. wordpress. com

INTRODUCTION TO EMBEDDED SYSTEMS • Classification based on Complexity and performance 1. Small-scale • • Simple applications where the performance requirements are not time-critical. Built around low performance and low cost 8 or 16 bit μp/μc. 2. Medium-scale • • Slightly complex in hardware and firmware requirement. Built around medium performance and low cost 16 or 32 bit μp/μc. 3. Large-scale • Highly complex hardware & firmware. • Built around 32 or 64 bit RISC μp/μc or PLDs or So. C or multi-core processors www. maheshelectronics. wordpress. com .

Features and architecture considerations • Basic elements of an embedded system: www. maheshelectronics. wordpress. com

Features and architecture considerations • System core: -Central processing unit This include: • Arithmetic logic unit (ALU), which performs computation. • Registers needed for the basic operation of the CPU, such as the program counter (PC), stack pointer (SP), and status register (SR). • Further registers to hold temporary results. • Instruction decoder and other logic to control the CPU, handle resets, and interrupts, and so on. www. maheshelectronics. wordpress. com

Features and architecture considerations • Memory for the program: Non-volatile (read-only memory, ROM), meaning that it retains its contents when power is removed. • Memory for data: Known as random-access memory (RAM) and usually volatile. • Input and output ports: To provide digital communication with the outside world. • Address and data buses: To link these subsystems to transfer data and instructions. • Clock: To keep the whole system synchronized. It may be generated internally or obtained from a crystal or external source; modern MCUs offer considerable choice of clocks. www. maheshelectronics. wordpress. com

Features and architecture considerations Common peripherals: - • Timers: Most microcontrollers have at least one timer because of the wide range of functions that they provide. • They provide a regular “tick” that can be used to schedule tasks in a program. Many programs are awakened periodically by the timer to perform some action—measure the temperature and transmit it to a base station, for example—then go to sleep (enter a low-power mode) until awakened again. This conserves power, which is vital in battery-powered applications. www. maheshelectronics. wordpress. com

Features and architecture considerations • Watchdog timer: This is a safety feature, which resets the processor if the program becomes stuck in an infinite loop. • Communication interfaces: A wide choice of interfaces is available to exchange information with another IC or system. They include serial peripheral interface (SPI), inter-integrated circuit (I²C or IIC), asynchronous (such as RS-232), universal serial bus (USB), controller area network (CAN), ethernet, and many others. www. maheshelectronics. wordpress. com

Features and architecture considerations • Non-volatile memory for data: This is used to store data whose value must be retained when power is removed. Serial numbers for identification and network addresses are two obvious candidates. • Analog-to-digital converter: This is very common because so many quantities in the real world vary continuously. www. maheshelectronics. wordpress. com

Features and architecture considerations • Digital-to-analog converter: This is much less common, because most analog outputs can be simulated using PWM. An important exception used to be sound, but even here, the use of PWM is growing in what are called class D amplifiers. • Real-time clock: These are needed in applications that must track the time of day. Clocks are obvious examples but data loggers are also an important case. www. maheshelectronics. wordpress. com

Features and architecture considerations • Monitor, background debugger, and embedded emulator: These are used to download the program into the MCU and communicate with a desktop computer during development. • The processor communicates with these peripherals by reading from, and writing to, particular addresses in memory. These memory locations are called special function registers or peripheral registers to distinguish them from ordinary memories, which simply store data, but exactly the same commands are used—no special commands are needed. In practice, microcontrollers spend much of their time handling the peripheral registers. www. maheshelectronics. wordpress. com

Features and architecture considerations • RISC Vs CISC : RISC (Reduced Instruction Set Computer)) Supports lesser number of instructions. CISC (Complex Instruction Set Computer) Supports greater number of instructions. Supports few addressing modes for memory access and data transfer Supports many addressing modes for memory access and data transfer instructions. Single, fixed length instructions Variable length instructions Instructions take fixed amounts of time for execution Instructions take varying amounts of time for execution Instruction pipelining works effectively and increases the execution Instruction pipelining concept is not effectively works as different sizes and speed. different execution times of instructions. Orthogonal instruction set (allows each instruction to operate on any Non-orthogonal set (all instructions are not allowed to operate on any register and use any addressing mode. ) register and use any addressing mode. Less silicon usage and decoding logic is not complex. More silicon usage since more additional decoder logic is required to implement the complex instruction decoding. Because of the simple instructions, the design of compiler is easy. Because of large amount of different and complex instructions, the design of compiler is complex. A larger number of registers are available. Limited no. of general purpose registers www. maheshelectronics. wordpress. com

Features and architecture considerations • HARVARD ARCHITECTURE Vs VON-NEUMANN ARCHITECTURE : It has separate buses for instruction as well as data fetching. This means that, the data memory and program memory are separated. It shares single common bus for instruction and data fetching. This means that only one set of addresses covers both data memory and program memory. The memory map shows the addresses at which each type of memory is located. www. maheshelectronics. wordpress. com

Low performance as compared to Harvard Easier to pipeline, so high performance can be achieve. architecture First fetches the instruction and then fetches the data. The two separate fetches It allows simultaneous access to the program and data memories. For instance, the CPU slows down the controller’s operation. can read an operand from the data memory at the same time as it reads the next Because several memory cycles are needed to extract a full instruction from the program memory, this architecture is intrinsically less efficient. Since data memory and program memory are stored physically in different locations, no chances exist for accidental corruption of program memory Accidental corruption of program memory may occur if data memory and program memory are stored physically in the same chip. A problem with the Harvard architecture is that constant data (often lookup tables) must be stored in the program memory because it is nonvolatile. This means that constants cannot be read in the same way as volatile values from the data memory. Special “table read” instructions must therefore be provided or part of the program memory is mapped into data memory The system is simpler and there is no difference between access to constant and variable data. Separate decoding logic is required, because separate buses and control signals are used for accessing data memory and program memory No additional logic is required because, Same bus and control signals are used for accessing for both data memory and program memory. Comparatively high cost Low cost www. maheshelectronics. wordpress. com

Features and architecture considerations MEMORY MAPPED I/O & I/O MAPPED I/O : I/O devices are mapped into the system memory map. i. e Common address space for memory and I/O ports (The I/O ports are viewed as memory locations and are addressed likewise) I/O devices are mapped into a separate address space. i. e. , there is separate address space for memory and I/O ports. www. maheshelectronics. wordpress. com

Different control signals are used for memory and I/O The control signals used for memory operation and I/O operation are operations. same. M/IO =1 for memory operation M/IO = 1 for both Memory and I/O operations M/IO =0 for I/O operation Less no. of instructions are for I/O access. ( only IN and OUT All instruction which can access memory can be used to access I/O instructions) ports. The data can be moved from any register to I/O port and vice-versa. The data transfer takes place between Accumulator and I/O port only The arithmetic, logic and bit manipulation instructions which are No instructions are available for direct manipulation of I/O data. available for data in memory can also be used for I/O operations. First the processor reads data from I/O port and then Hence the processor can directly manipulate data from I/O port. manipulates. Large number of I/O devices can be interfaced Less no. of I/O devices can be interfaced Full address space can’t be used for addressing Memory, because some Full address space can be used for addressing Memory, because locations are allotted for I/O ports. I/O locations are separated from memory. The entire address bus must be fully decoded for every device, which Less logic is needed to decode a discrete address and therefore increases the cost less cost www. maheshelectronics. wordpress. com

Features and architecture considerations LITTLE-ENDIAN & BIG-ENDIAN PROCESSORS Endianness specifies the order which the data is stored in the memory by processor operations in a multi byte system. Little-endian means lower order data byte is stored in memory at the lowest address and the higher order data byte at the highest address. Big-endian means the higher order data byte is stored in memory at the lowest and the lower order data byte at the highest address. 2000 H 2001 H 2002 H 2003 H www. maheshelectronics. wordpress. com

INTRODUCTION TO MSP 430 MICROCONTROLLERS: • MAIN CHARACTERISTICS OF MSP 430 MICROCONTROLLER • • • Flash (or) ROM-based low-power MCUs CPU clock : 8/16 MHz Operating voltage : 1. 8– 3. 6 V Power specification overview, as low as: 0. 1 μA RAM retention 0. 7 μA real-time clock mode operation 160 - 250 µA/MIPS at active operation Fast wake-up from standby mode in less than 1 µs. Device parameters – Flash/ ROM options: 1 KB – 60 KB – RAM options: 128 B– 8 KB www. maheshelectronics. wordpress. com – GPIO options: 14 - 80 pins

INTRODUCTION TO MSP 430 MICROCONTROLLERS: • • • • • Other integrated peripherals: 10/12/16 -bit Analogue-to-Digital Converter (ADC); 12 -bit dual Digital-to-Analogue Converter (DAC); Comparator-gated Timers; Watch Dog Timer SPI, I 2 C, UART Operational Amplifiers (OP Amps) 16× 16 multiplier Comparator_A Temp. sensor LCD driver Supply Voltage Supervisor (SVS) Brown out Reset 16 bit RISC CPU: Instructions processing on either bits, bytes or words; Compact core design reduces power consumption and cost; Compiler efficient; 27 core instructions; 7 addressing modes; www. maheshelectronics. wordpress. com Extensive vectored-interrupt capability.

BLOCK DIAGRAM OF MSP 430 F 2013/ F 2003 MICROCONTROLLER www. maheshelectronics. wordpress. com

MSP 430 part numbering: www. maheshelectronics. wordpress. com

VARIANTS OF MSP 430 FAMILY – 1 XX, 2 XX, 3 XX, 4 XX, 5 XX: VARIANT OF FAMILY POWER SPECIFICATIONS DEVICE PARAMETERS OTHER INTEGRATED PERIPHERALS MSP 430 x 1 xx 0. 1 μA RAM retention 0. 7 μA real-time clock mode 200 μA / MIPS active Features fast wake-up from standby mode in less than 6 µs. Flash/ROM options: 1– 60 KB RAM options: 128 B– 2 KB GPIO options: 14/22/48 pins ADC options: Slope, 10 & 12 -bit SAR 12 -bit DAC, up to 2 16 -bit timers, WDT, brown-out reset, SVS, USART module (UART, SPI), DMA, 16× 16 multiplier, Comparator_A, Temp. sensor MSP 430 F 2 xx 0. 1 μA RAM retention 0. 3 μA standby mode (VLO) 0. 7 μA real-time clock mode 220 μA / MIPS active Feature ultra-fast wake-up from standby mode in less than 1 μs Flash/ROM options: 1 KB– 60 KB RAM options: 128 B – 8 KB GPIO options: 10/16/24/32/48 pins ADC options: Slope, 10 & 12 -bit SAR, 16 & 24 -bit Sigma Delta operational amplifiers, 12 -bit DAC, up to 2 16 -bit timers, watchdog timer, brown-out reset, SVS, USI module (I²C, SPI), USCI module, DMA, 16× 16 multiplier, Comparator_A+, Temperature sensor MSP 430 x 3 xx 0. 1 μA RAM retention 0. 9 μA real-time clock mode 160 μA / MIPS active Features fast wake-up from standby mode in less than 6 µs. ROM options: 2– 32 KB RAM options: 512 B– 1 KB GPIO options: 14/40 pins ADC options: Slope, 14 -bit SAR LCD controller, multiplier MSP 430 x 4 xx 0. 1 μA RAM retention 0. 7 μA real-time clock mode 200 μA / MIPS active Features fast wake-up from standby mode in less than 6 µs. Flash/ROM options: 4 KB– 60 KB RAM options: 256 B – 8 KB GPIO options: 14/32/48/56/68/72/80 pins ADC options: Slope, 10 & 12 -bit SAR, 16 -bit Sigma Delta 12 -bit DAC, Op Amps, RTC, up to two 16 -bit timers, watchdog timer, basic timer, brown-out reset, SVS, USART module (UART, SPI), USCI module, LCD Controller, DMA, 16× 16 & 32 x 32 multiplier, Comparator_A, Temp. sensor MSP 430 x 5 xx 0. 1 μA RAM retention 2. 5 μA real-time clock mode 165 μA / MIPS active Features fast wake-up from standby mode in less than 5 µs. Flash options: up to 512 KB RAM options: up to 66 KB ADC options: 10 & 12 -bit SAR GPIO options: 29/31/47/48/63/67/74/87 pins High resolution PWM, 5 V I/O's, USB, backup battery switch, up to 4 16 -bit timers, watchdog timer, Real-Time Clock, brown-out reset, SVS, USCI module, DMA, 32 x 32 multiplier, Comp B, temperature sensor MSP 430 x 6 xx 0. 1 μA RAM retention 2. 5 μA real-time clock mode 165 μA / MIPS active Features fast wake-up from standby mode in less than 5 µs. Flash options: up to 512 KB RAM options: up to 66 KB ADC options: 10 & 12 -bit SAR GPIO options: 74/90 pins USB, LCD, DAC, Comparator_B, DMA, 32 x 32 multiplier, power management module (BOR, SVS, SVM, LDO), watchdog timer, RTC, Temp sensor www. maheshelectronics. wordpress. com

Memory map of MSP 430 www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • The cpu features – Calculated branching – Table processing – 27 RISC instructions – 7 addressing modes – All instructions use all the addressing modes – Full register access – Single cycle register operations (RISC) – Direct memory-to-memory transfers – Constant generator provides most used values www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers There are 16 registers Ø Contents are 16 -bits Ø User has access to all registers Ø 4 registers are special purpose Note bus structure Ø MDB – Memory Data Bus Ø MAB – Memory Address Bus Ø Also have 2 internal bussed to deliver 2 operand to ALU Diagram is called the datapath of the processor www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • R 4 thru R 15 – Registers are indistinguishable – Can be used as • Data Registers • Address Registers • Index values – Can be accessed with byte or word instructions – There is Register-Byte operation and Byte-Register operation – covered later www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • R 0: Program Counter (PC) : • The 16 -bit Program Counter (PC/R 0) points to the next instruction to be fetched from memory and executed by the CPU. • The Program counter is incremented by the number of bytes used by the instruction (2, 4, or 6 bytes, always even). www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • R 1: Stack Pointer (SP) • The stack memory is a memory block where the data is stored in LIFO manner. • The Stack Pointer (SP/R 1) holds the address of the stack-top. • In the MSP 430, as in many other processors, the stack is allocated at the top of the RAM and grows down towards low addresses. www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • Operation of the Stack : The operation of the stack is illustrated in the following figure. The specific addresses are for MSO 430 F 2013 with 128 Bytes of RAM are from 0 x 0200 to 0 x 027 F. Hence, Before the execution, the initially the value of SP = 0 x 0280 www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • R 2: Status Register (SR) • The Status Register (SR/R 2) stores the status bits and control bits. • C : Carry Flag Z : Zero Flag • N : Negative Flag V: Signed overflow flag www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • Enable Interrupts : : Setting the general interrupt enable (GIE) bit enables maskable interrupts. • Clearing the bit disables all maskable interrupts. • There also nonmaskable interrupts, which cannot be disabled with GIE. www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • Control of Low-Power Modes : • SCG 1 (System clock generator 1) : When set, turns off the SMCLK. • SCG 0 (System clock generator 0) : When set, turns off the DCO dc generator, if DCO-CLK is not used for MCLK or SMCLK. • OSCOFF (Oscillator OFF ) : When set, turns off the LF XT 1 crystal oscillator, • if LFXT 1 -CLK is not used for MCLK or SMCLK. • CPUOFF : When set, turns off the CPU. www. maheshelectronics. wordpress. com

MSP 430 –CPU architecture & registers • R 2/R 3: Constant Generator Registers (CG 1/CG 2) • • • Depending of the source-register addressing modes (As) value, six commonly used constants can be generated without a code word or code memory access to retrieve them. The constants below are chosen based on the bit (As) of the instruction that selects the addressing mode. Register Addressing mode R 2 R 3 R 3 Constant 10 +4 11 +8 00 0 01 +1 10 +2 11 -1 (FFFF) www. maheshelectronics. wordpress. com

MSP 430 –Addressing modes • MSP 430 addressing modes – Addressing mode – the way in which the operand(s) of an instruction are accessed, i. e. , the effective addresses are calculated. – 7 modes supported • Register Mode – (Rn) – operands are in registers • Immediate Mode – #N – The operand is part of the instruction – Instructions have format OPCODE #OPERAND • Absolute Mode – &ADDR – The address of the operand is given by the word following the opcode – Instructions have format OPCODE &ADDRESS www. maheshelectronics. wordpress. com

MSP 430 –Addressing modes • Remainder of addressing mode – Indexed Mode – X(Rn) – (Rn+X) points to (is the address of) the operand. The value X is the next word in the instruction stream after the OPCODE. – Symbolic Mode – ADDR – (PC+X) points to the operand. X is the next word. – Indirect Register Mode - @Rn – Rn is used as a pointer to the operand. – Indirect Autoincrement - @Rn+ - Rn is used as a pointer to the operand. After access Rn is incremented by 1 for . B instructions and by 2 for. W instructions www. maheshelectronics. wordpress. com

INSTRUCTION FORMATS OF MSP 430 : • Each instruction has 2 - parts: • The task to be performed – called as Operation code (Opcode) • The data to be operated on – called as Operand. • Instruction format: OPCODE OPERAND • There are three core-instruction formats: » Dual-operand » Single-operand » Jump www. maheshelectronics. wordpress. com

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INSTRUCTION SET OF MSP 430 • The instructions can be classified as follows: 1. Movement Instructions (Data Transfer) 2. Arithmetic and Logic Instructions 3. Shift and Rotate Instructions 4. Control Transfer instructions (Branch/Subroutine/Interrupt) www. maheshelectronics. wordpress. com

Movement Instructions (Data Transfer) Instruction Operation Example Copies data from source to destination 1 mov. w R 5, R 6 mov. w src, dst src Push data onto stack 2 push. w src push. w R 5 ( first the SP is decremented by 2 and the source content is stored at stacktop) @ --SP = src Pop data from stack 3 pop. w dst R 6 R 5 @ SP R 5 push. w R 6 ( first the content of stacktop is moved to destination and SP is incremented by 2) dst = @SP + + www. maheshelectronics. wordpress. com SP-2 R 6 @ SP SP SP+2

Arithmetic and Logic Instructions Binary Arithmetic Instructions with Two operands Instruction Operation Example Add the content of source to destination 1 add. w src, dst add. w R 5, R 6 dst + src Add with carry 2 addc. w src, dst addc. w R 5, R 6 dst + (src + C) Add carry bit to the destination 3 adc. w dst adc. w R 6 dst + C Subtract the content of source from destination 4 sub. w src, dst sub. w R 5, R 6 dst - src Subtract with borrow 5 subc. w src, dst subc. w R 5, R 6 dst –( src + C) Subtract borrow bit from the destination 6 sbc. w dst sbc. w R 6 dst – C Compares source and destination. 7 cmp. w src, dst Performs ( dst – src), but Only flags are changed If dst > src : C=0, Z=0 If dst < src : C=1, Z=0 www. maheshelectronics. wordpress. com If dst = src : C=0, Z=1 cmp. w R 5, R 6

Arithmetic Instructions with One operand Instruction Operation Example Clear destination 1 clr. w R 6 clr. w dst 0 The content of destination is decremented by 1 2 R 6 0 dec. w R 6 dec. w dst – 1 R 6 - 1 Double decrement decd. w R 6 3 decd. w dst The content of destination is decremented by 2 R 6 – 2 dst – 2 The content of destination is inccremented by 1 4 inc. w R 6 inc. w dst + 1 R 6 + 1 Double increment incd. w R 6 5 incd. w dst The content of destination is inccremented by 2 R 6 + 2 dst + 2 Test ( compare with zero) 6 tst. w dst Performs ( dst – 0), but Only flags are changed If dst > 0 : C=0, Z=0 If dst < 0 : C=1, Z=0 www. maheshelectronics. wordpress. com If dst = 0 : C=0, Z=1 tsd. w R 6

Decimal Arithmetic & logical Instructions These instructions are used to perform BCD addition Instruction Operation Example Perfroms the decimal addtion of destination and source with carry 1 dadd. w R 5, R 6 dadd. w src, dst + src + C Performs the decimal addition of destination and carry. 2 R 6 + R 5+C dadc. w R 6 dadc. w dst + C R 6 + C Logic Instructions with ONE operand Instruction Operation Example Invert destination 1 inv. w dst Performs bit-wise NOT operation (1’s complement) inv. w R 6 dst ~dst www. maheshelectronics. wordpress. com

Logic Instructions with Two operands Instruction Operation Example Performs bit-wise logic AND operation 1 and. w src, dst and. w R 5, R 6 dst AND src Performs bit-wise logic Ex-OR operation 2 xor. w src, dst xor. w R 5, R 6 dst XOR src Performs bit-wise Test operation 3 bit. w src, dst bit. w R 5, R 6 It performs Logic AND operation, But Only flags are affected Set bits in destination 4 bis. w src, dst The source operand the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. bis. w R 5, R 6 dst OR src Clear bits in destination 5 bic. w src, dst The inverted source operand the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected dst AND ~src www. maheshelectronics. wordpress. com bic. w R 5, R 6

Byte manipulation Instruction 1 swpb dst Operation Example Swap upper and lower bytes The high and the low byte of the operand are exchanged swpb R 6 dst. 15: 8 ↔ dst. 7: 0 2 sxt dst Extend sign of lower byte The sign of the low byte of the operand is extended into the high byte dst. 15: 8 dst. 7 If dst. 7 = 0: high byte = 00 H afterwards If dst. 7 = 1: high byte = FF H afterwards www. maheshelectronics. wordpress. com sxt R 6

Operations on Bits in Status Register These instructions are used to set or clear the flags in Status Register. All these instructions are emulated instructions. Instruction Operation Flag affected 1 clrc Clear Carry bit C = 0 2 clrn Clear Negative bit N = 0 3 clrz Clear Zero bit Z = 0 4 setc Set Carry bit C = 1 5 setn Set Negative bit N = 1 6 setz Set Zero bit Z = 1 7 dint Disable General Interrupts GIE = 0 8 eint www. maheshelectronics. wordpress. com Enable General Interrupts GIE = 1

Shift and Rotate Instructions Instruction Description rla dst Arithmetic shift Left rra dst Arithmetic shift Right rlc dst Rotate Left through Carry rrc dst Rotate Right through Carry Operation www. maheshelectronics. wordpress. com

Control Transfer Instructions Instruction 1 br src Description Operation Branch ( go to) PC src 2 3 call src ret Call Subroutine SP SP-2 @ SP PC PC src Return from Subroutine PC @ SP SP SP+2 4 5 reti nop SR @ SP SP SP+2 PC @ SP SP SP+2 Return from Interrupt No operation ( consumes single cycle ) www. maheshelectronics. wordpress. com

JUMP Instructions 1 jmp label 2 jc / jlo label Unconditional Jump if carry / Jump if lower Jump if C =1 Jump if C =0 3 jnc / jhs label Jump if not carry / Jump higher or same 4 Jz / jeq label Jump if zero / Jump if equal Jump if Z =1 5 Jnz / jne label Jump if not zero / Jump if not equal Jump if Z =0 6 jn label Jumpif negative Jump if N =1 7 jge label Jump if greater or equal (signed values) Jump if (N xor V) =0 8 jl label Jump if less than (signed values) www. maheshelectronics. wordpress. com Jump if (N xor V) =1

Sample Embedded system on MSP 430 www. maheshelectronics. wordpress. com