Embedded System Designing AVR Microcontroller Introduced by Eng

Embedded System Designing AVR Microcontroller Introduced by: Eng. Abd-Elsalam Boda_eng@hotmail. com

Course Outline Introduction. AVR microcontroller Architecture. C Review. Memories in AVR. I/O Ports. Interrupts, “External Interrupts”. Timers/Counters Timer/counter 0 … 8 bit timer/counter. Timer/counter 1 … 16 bit timer/counter. Timer/counter 2 … 8 bit timer/counter. Analog comparator “AC”. Analog to digital converter “A/D”. Serial peripheral interface “SPI”. USART. Two wire serial interface “I 2 C”. Applications “According to the course flow”.

Introduction ØMicroprocessor vs. Microcontroller RAM ROM Microcontroller Serial & Parallel Ports Micro. Processor Timer I/O Port Interrupt

Introduction Microprocessor: Faster. General purpose. Expensive CPU is stand-alone, RAM, ROM, I/O, timer are separate. Designer can control the amount of ROM, RAM and I/O ports. It is cheaper compared to the microcontroller with the same features.

Introduction Microcontroller: Slower. Stand alone operation. Cheaper. CPU, RAM, ROM, I/O and timer are all on a single chip(but fixed amount). for applications in which cost, power and space are critical. Single Operation.

Introduction Memory types: There are several types of memory which is divided into RAM (Volatile ) and ROM and Flash memory (Non-Volatile) and each type is divided into sub types as follows: RAM(Random Access Memory): ○ SRAM(Static RAM): Very expensive Very high performance Constructed of Flip-Flops

Introduction RAM(Random Access Memory): ○ DRAM(Dynamic RAM): Cheap Constructed from Capacitors so it needs to be refreshed periodically. It is divided into: SDRAM(Synchronous DRAM) - SDR-SDRAM(Single Data Rate) - DDR-SDRAM(Double Data Rate) ○ DDR-SDRAM has better performance and faster than the SDR-SDRAM and it is commonly used now in our computer

Introduction ROM(Read Only Memory): ○ ROM(ROM) ○ PROM(Programmable ROM). ○ EPROM (Erasable PROM). ○ EEPROM(Electrically Erasable PROM).

Introduction Flash Memory: ○ It is non-volatile computer memory that can be electrically erased and reprogrammed. It is a technology that is primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. It is a specific type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that is erased and programmed in large blocks

Introduction LEDS and Switches: LED(Light Emitting Diode): ○ A light-emitting diode (LED) is a semiconductor diode that emits light when an electrical current is applied in the forward direction of the device, as in the simple LED circuit.

Introduction Switches. ○ Switches type: Toggle switch. Pushbutton switch. DIP switch.

Introduction Switches ○ The shown circuit is a sample switch active low circuit, when we press on the pushbutton the ATMEL pin will be connected to the ground, otherwise it will be connected to the VCC

Introduction Opto-isolators and Opto-couplers The Opto-coupler consists of the control part which is the photo-diode and the load part which is the photo-transistor. When the voltage is applied on the photo-diode, it emits light which turns the photo-transistor on (be in the saturation mode “short circuit”). It is very fast The Switch ON/OFF speed is up to 120 MHz with high Performance Opto-Coupler.

Introduction Relays ○ All Relays Operate Using the same principle. ○ Consisted of a control circuit ○ has a coil “in the green color” and a load circuit that has a switch “ in the red color”.

Introduction Buffers: ○ Buffers are used to protect IC’s from high current because it passes voltage and holds current ○ Also data buffer is a region of memory used to temporarily hold data while it is being moved from one place to another. ○ Buffers IC’s like 74244, 74245.

AVR microcontrol ler Architecture.

ATmega 16 Features From the data Sheet.

C Review: Include Files: “according to Codevision” AVR header files e. g. mega 8535, mega 16, 902313, tiny 22, …ect. C header files e. g. math. h, string. h, stdlib. h, stdio. h, . . . ect. Other useful header files e. g. Delay. h, lcd. h, spi. h, I 2 C. h, Gray. h, …ect.

C Review: C functions C main function must be endless. Other function could be used. ○ Function prototype declaration. Return-type function-name(Arguments or “the inputs”); ○ Function itself. Return-type function-name(Arguments or “the inputs”) { }

C Review: Variable Declaration: Type Size (Bits) bit 1 char 8 unsigned char 8 int 16 short int 16 unsigned int 16 Range 0, 1 -128 to 127 0 to 255 -128 to 127 -32768 to 32767 0 to 65535 -32768 to 32767

C Review: Variable Declaration: Type long int Size (Bits) 32 unsigned long int 32 32 float 32 double 32 Range -2147483648 to 2147483647 0 to 4294967295 -2147483648 to 2147483647 ± 1. 175 e-38 to ± 3. 402 e 38

C Review: Operators: Assignment operator (x=y) … (+=, -=, /=, *=) Increment/decrement operator ++/- Equal operator (==) Less than (<) … less than or equal (<=) Greater than (>) … less than or equal (>=) Not equal (!=) Logical operators: ○ And (&&) Bitwise AND (&) ○ Or (||) Bitwise OR(|) ○ Not (!) Bitwise XOR(^) ○ Complement (~) ○ Right shifted (>>) … Left shifted (<<)

C Review: If Statement: If(condition is true) { Do whatever here… } Else if (another condition is true) { Do whatever here… } : . Else { Do a default operation } If there are no braces the next statement is the only statement under the condition

C Review: The For statement If there are no braces the next For(initial; condition ; increment) statement is the only statement { under the for statement Do whatever here… } for (count = 100; count > 0; count--) for (count = 0; count < 1000; count += 5) count = 1; for (x=5 ; count < 1000; count++) for (count = 0; count < 100; ) {count++; } for (i = 0, j = 999; i < 1000; i++, j--) b[j] = a[i];

C Review: While statement While(condition) { Do whatever here… } Do { }while(condition);

C Review: Arrays: ○ Char arr 1[5]; ○ Char arr 2[]=“legend”; ○ Char arr 1[5]={1, 2, 3, 4, 5}; ○ Arr 1[5] … from arr 1[0] to arr 1[4] ○ Indexed by integer. ○ Tow dimensional array x[4][3]; Pointers ○ Char *x; ○ x++; ○ Char x; char *x=“legend”; *x++; &x++;

ATmega 16 Pin description: 4 ports A, B, C, D each has 8 pins. RESET input. A low level on this pin for longer than the minimum pulse length will generate a reset. XTAL 1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL 2 Output from the inverting Oscillator amplifier. AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC. AREF is the analog reference pin for the A/D Converter.

ATmega 16 Status Register Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions. #asm(‘’sei”); #asm(“cli”);

ATmega 16 Status Register Bit 6 – T: Bit Copy Storage Bit 5 – H: Half Carry Flag Bit 4 – S: Sign Bit, S = N ^ V Bit 3 – V: Two’s Complement Overflow Flag Bit 2 – N: Negative Flag Bit 1 – Z: Zero Flag

ATmega 16 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The AVR Stack Pointer is implemented as two 8 -bit registers.

ATmega 16 Memories In-System Reprogrammable Flash Program Memory The ATmega 16 contains 16 K bytes On-chip In-System Reprogrammable Flash memory for program storage. The Flash is organized as 8 K x 16. The Flash memory has an endurance of at least 10, 000 write/erase cycles. The ATmega 16 Program Counter (PC) is 13 bits wide.

ATmega 16 Memories SRAM Data Memory 1120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM.

ATmega 16 Memories EEPROM Data Memory The ATmega 16 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100, 000 write/erase cycles. EEPROM Read/Write Access There a several registers we will deal with: ○ The EEPROM Address Register – EEARH and EEARL. ○ The EEPROM Data Register – EEDR. ○ The EEPROM Control Register – EECR.

ATmega 16 Memories The EEPROM Address Register – EEARH and EEARL. EEPROM Data Register – EEDR.

ATmega 16 Memories The EEPROM Control Register – EECR. ○ Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I -bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

ATmega 16 Memories The EEPROM Control Register – EECR. ○ Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one cause the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

ATmega 16 Memories The EEPROM Control Register – EECR. ○ Bit 1 – EEWE: EEPROM Write Enable. The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place.

ATmega 16 Memories The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

ATmega 16 Memories Cautions: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

ATmega 16 Memories Cautions: When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set; the CPU is halted for two cycles before the next instruction is executed.

ATmega 16 Memories The EEPROM Control Register – EECR. ○ Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately.

ATmega 16 Memories Cautions: ○When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. ○The user should poll the EEWE bit before starting the read operation. ○ If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

$ATmega 16 Memories void EEPROM_write(unsigned int ui. Address, unsigned char uc. Data) { /*$

ATmega 16 Memories void EEPROM_write(unsigned int ui. Address, unsigned char uc. Data) { /* Wait for completion of previous write */ while(EECR & (1<<EEWE)); /* Set up Address and Data Registers */ EEAR = ui. Address; EEDR = uc. Data; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); }

$ATmega 16 Memories unsigned char EEPROM_read(unsigned int ui. Address) { /* Wait for completion$

ATmega 16 Memories unsigned char EEPROM_read(unsigned int ui. Address) { /* Wait for completion of previous write */ while(EECR & (1<<EEWE)); /* Set up Address Register */ EEAR = ui. Address; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; }

ATmega 16 I/O Ports Three I/O memory address locations are allocated for each port, one each for the Data Register, Data Direction Register, and the Port Input Pins. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

ATmega 16 I/O Ports If PORTxn is written a logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. If PORTxn is written a logic one when the pin is configured as an output pin, the port pin is driven high. If PORTxn is written a logic zero when the pin is configured as an output pin, the port pin is driven low. Reading the Pin Value: Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit.

ATmega 16 I/O Ports Register Description for I/O-Ports: Port A Data Register – PORTA Port A Data Direction Register - DDRA Port A Input Pins Address – PINA

ATmega 16 I/O Ports I/O ports registers are bit-addressable registers, in codevision you can use this feature… If you want to get the second bit in the register DDRA you simply say DDRA. 1. If you intend to use IAR compiler - or any other compiler- you need first to declare the I|O ports that you’ll use as bitaddressable register as following: Method 1 Unsigned char porta @ port 0 x 3 b; SFR PORTA =0 x 3 b; #define PORTA (*(volatile unsigned char*)0 x 3 b) #define bit(x) (1<<(x)) DDRA |= bit(1); /*set*/ DDRA &= ~bit(1); // clear DDRA ^= bit(1); // complement.

ATmega 16 I/O Ports Method 1 #define bit(x) (1<<(x)) #define setbit(P, B) (P)|= bit(B); /*set*/ #define clrbit(P, B) (P) &= ~bit(B); //clear #define cmpbit(P, B) (P)^= bit(B); // complement. Method 2 Typedef struct { unsigned bit 0 : 1, bit 1 : 1, bit 2 : 1, bit 3 : 1, bit 4 : 1, bit 5 : 1, bit 6 : 1, bit 7 : 1, }IOREG; #define PORTA(*(IOREG *)0 x 3 B) Int i=PORTA. bit 1; PORTA. bit 1=0;

ATmega 853 5 Interrupts

ATmega 1 6 Interrupts

ATmega 16 Interrupts // Interrupt definitions for code vision interrupt [program address] void my_function(void) { // Place your code here } // Interrupt definitions for IAR #pragma vector= program address __interrupt void my_function(void) { // Place your code here }

ATmega 16 External interrupts The ATmega 16 or ATmega 8535 has three interrupt INT 0, INT 1 and INT 2 … each of them could be activated on the rising and/or falling edge or level sensed. To enable any interrupt of them the GICR is used. To select the mode of sensing the MCUCR & MCUCSR is used. To sense the occurrence of the interrupt the CIFR is used. General Interrupt Control Register – GICR

ATmega 16 External interrupts MCU Control Register – MCUCR

ATmega 16 External interrupts MCU Control and Status Register – MCUCSR Bit 6 – ISC 2: Interrupt Sense Control 2 The asynchronous External Interrupt 2 is activated by the external pin INT 2 if the SREG I-bit and the corresponding interrupt mask in GICR are set. If ISC 2 is written to zero, a falling edge on INT 2 activates the interrupt. If ISC 2 is written to one, a rising edge on INT 2 activates the interrupt. Edges on INT 2 are registered asynchronously. When changing the ISC 2 bit, an interrupt can occur. Therefore, it is recommended to first disable INT 2 by clearing its Interrupt Enable bit in the GICR Register. Then, the ISC 2 bit can be changed. Finally, the INT 2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF 2) in the GIFR Register before the interrupt is re-enabled.

ATmega 16 External interrupts #include <mega 8535. h> // External Interrupt 0 service routine interrupt [EXT_INT 0] void ext_int 0_isr(void) { // Place your code here PORTC++; } void main(void) { PORTC=0 x 00; DDRC=0 x. FF; GICR|=0 x 40; MCUCR=0 x 02; MCUCSR=0 x 00; GIFR=0 x 40; #asm("sei") while (1); }

8 -bit Timer/Counter 0 with PWM Timer/Counter 0 is a general purpose, single channel, 8 -bit Timer/Counter module. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source, The Timer/Counter is inactive when no clock source is selected When no clock source is selected the timer is stopped. The clock source is selected by the Clock Select logic which is controlled by the clock select (CS 02: 0) bits located in the Timer/Counter Control Register (TCCR 0). Timer/Counter Interrupt Mask Register – TIMSK : to Enable the timer interrupts. Timer/Counter Interrupt Flag Register – TIFR: to monitor the timer interrupts Timer/counter Register (TCNT 0): hold the count value Output compare Register (OCR 0): hold the value to be compared with the value in TCNT 0.

8 -bit Timer/Counter 0 with PWM Timer/Counter Register (TCNT 0) Output Compare Register (OCR 0)

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: The mode of operation, i. e. , the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM 01: 0) and Compare Output mode (COM 01: 0) bits.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: Normal Mode: In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8 -bit value and then restarts from the bottom (0 x 00). In normal operation the Timer/Counter Overflow Flag (TOV 0) will be set in the same timer clock cycle as the TCNT 0 becomes zero. The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: CTC Mode “Clear Timer On Compare”: In CTC mode the counter is cleared to zero when the counter value (TCNT 0) matches the OCR 0. The OCR 0 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The counter value (TCNT 0) increases until a Compare Match occurs between TCNT 0 and OCR 0, and then counter (TCNT 0) is cleared. An interrupt can be generated each time the counter value reaches the TOP value by using the OCF 0 Flag.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: For generating a waveform output in CTC mode, the OC 0 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM 01: 0 = 1). The OC 0 value will not be visible on the port pin unless the data direction for the pin is set to output.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 The waveform generated will have a maximum frequency of f. OC 0 = fclk_I/O/2 when OCR 0 is set to zero (0 x 00). The waveform frequency is defined by the following equation: The “N” variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the normal mode of operation, the TOV 0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0 x 00.

8 -bit Timer/Counter 0 with PWM In CTC Mode:

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: Fast PWM Mode: The fast Pulse Width Modulation or fast PWM mode (WGM 01: 0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation (saw-tooth wave form). The counter counts from BOTTOM to MAX then restarts from BOTTOM. The generated wave form change from zero volt to five volt, then reset to zero.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: Fast PWM Mode - In non-inverting Compare Output mode, the Output Compare (OC 0) is cleared on the Compare Match between TCNT 0 and OCR 0, and set at BOTTOM. - In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM.

8 -bit Timer/Counter 0 with PWM In Fast PWM Mode the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: Phase Correct PWM Mode: The phase correct PWM mode (WGM 01: 0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation (triangular wave form). The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: Phase Correct PWM Mode: In non-inverting Compare Output mode, the Output Compare (OC 0) is cleared on the Compare Match between TCNT 0 and OCR 0 while upcounting, and set on the Compare Match while down-counting. In inverting Output Compare mode, the operation is inverted.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Modes of Operation: Phase Correct PWM Mode: The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits.

8 -bit Timer/Counter 0 with PWM In phase correct PWM mode: the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT 0 value will be equal to MAX for one timer clock cycle.

8 -bit Timer/Counter 0 with PWM Timer/Counter Control Register – TCCR 0 Bit 7 – FOC 0: Force Output Compare The FOC 0 bit is only active when the WGM 00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR 0 is written when operating in PWM mode. When writing a logical one to the FOC 0 bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC 0 output is changed according to its COM 01: 0 bits setting. Note that the FOC 0 bit is implemented as a strobe. Therefore it is the value present in the COM 01: 0 bits that determines the effect of the forced compare. A FOC 0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR 0 as TOP.

8 -bit Timer/Counter 0 with PWM Timer/Counter Interrupt Mask Register – TIMSK Bit 0 – TOIE 0: Timer/Counter 0 Timer Overflow Interrupt Enable Bit 1 – OCIE 0: Timer/Counter 0 Output Compare Match Interrupt Enable

8 -bit Timer/Counter 0 with PWM Timer/Counter Interrupt Flag Register – TIFR Bit 0 – TOV 0: Timer/Counter 0 Overflow Flag Bit 1 – OCF 0: Output Compare Flag 0

16 -bit Timer/Counter 1 The 16 -bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: True 16 -bit Design (i. e. , Allows 16 -bit PWM) Two Independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceller Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four Independent Interrupt Sources (TOV 1, OCF 1 A, OCF 1 B, and ICF 1)

16 -bit Timer/Counter 1 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source, The Timer/Counter is inactive when no clock source is selected When no clock source is selected the timer is stopped. The clock source is selected by the Clock Select logic which is controlled by the clock select (CS 02: 0) bits located in the Timer/Counter Control Register (TCCR 1 B). The Mode of operation is selected by (TCCR 1 A) and (TCCR 1 B). Timer/Counter Interrupt Mask Register – TIMSK : to Enable the timer interrupts. Timer/Counter Interrupt Flag Register – TIFR: to monitor the timer interrupts Timer/counter Register (TCNT 1)hold the count value Output compare Register (OCR 1 A/B): hold the value to be compared with the value in TCNT 0. The input capture unit capture the timer value in the Input capture register (ICR 1). Each of (TCNT 1, OCR 1 A, OCR 1 B, ICR 1) is a 16 -bit register divided into high and low.

8 -bit Timer/Counter 1 – TCNT 1 H and TCNT 1 L Output Compare Register 1 A (OCR 1 AH and OCR 1 AL) Output Compare Register 1 B (OCR 1 BH and OCR 1 BL)

8 -bit Timer/Counter 1 Input Capture Register 1 (ICR 1 H and ICR 1 L) When ever edge change is occurred on the ICP 1 the value of the timer which is in the TCNT 1 will be copied in the ICR 1. the Analog comparator output (ACO) in The Analog comparator control and status Register (ACSR) could be used in stead of the ICP to trigger the input capture unit.

8 -bit Timer/Counter 1 Control Register A – TCCR 1 A Bits from 7: 4 in Non PWM modes.

8 -bit Timer/Counter 1 Control Register A – TCCR 1 A Bits from 7: 4 in Fast PWM modes.

8 -bit Timer/Counter 1 Control Register A – TCCR 1 A Bits from 7: 4 in Phase correct PWM modes.

8 -bit Timer/Counter 1 Control Register A – TCCR 1 A Bit 3 – FOC 1 A: Force Output Compare for Channel A Bit 2 – FOC 1 B: Force Output Compare for Channel B it is the value present in the COM 1 x 1: 0 bits that determine the effect of the forced compare. A FOC 1 A/FOC 1 B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR 1 A as TOP. FOC 1 A/FOC 1 B bits are always read as zero.

8 -bit Timer/Counter 1 Control Register B – TCCR 1 B Wave Generation Mode Bits WGM 13: 10

8 -bit Timer/Counter 1 Wave Generation Mode Bits

8 -bit Timer/Counter 1 Control Register B – TCCR 1 B Bits from 0: 2 are the clock Select bits as in timer 0. Bit 7 – ICNC 1: Input Capture Noise Canceler Bit 6 – ICES 1: Input Capture Edge Select

8 -bit Timer/Counter 1 Timer/Counter Interrupt Mask Register – TIMSK(1) Timer/Counter Interrupt Flag Register – TIFR

8 -bit Timer/Counter 1 Modes of Operation: Normal Mode: The simplest mode of operation is the Normal mode (WGM 13: 0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16 -bit value (MAX = 0 x. FFFF) and then restarts from the BOTTOM (0 x 0000). In normal operation the Timer/Counter Overflow Flag (TOV 1) will be set in the same timer clock cycle as the TCNT 1 becomes zero. The output compare units can be used to generate interrupts at some given time. Using the output compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

8 -bit Timer/Counter 1 Modes of Operation: Clear Timer on Compare: In Clear Timer on Compare or CTC mode (WGM 13: 0 = 4 or 12), the OCR 1 A or ICR 1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT 1) matches either the OCR 1 A (WGM 13: 0 = 4) or the ICR 1 (WGM 13: 0 = 12). The OCR 1 A or ICR 1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.

8 -bit Timer/Counter 1 Modes of Operation: Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM 13: 0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.

8 -bit Timer/Counter 1 Modes of Operation: Phase Correct PWM Mode. The phase correct Pulse Width Modulation or phase correct PWM mode (WGM 13: 0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0 x 0000) to TOP and then from TOP to BOTTOM. The PWM resolution for the phase correct PWM mode can be fixed to 8 -, 9 -, or 10 -bit, or defined by either ICR 1 or OCR 1 A. The minimum resolution allowed is 2 -bit (ICR 1 or OCR 1 A set to 0 x 0003), and the maximum resolution is 16 -bit (ICR 1 or OCR 1 A set to MAX).

8 -bit Timer/Counter 1 Modes of Operation: Phase Correct PWM Mode.