Embedded RealTime Systems Lecture Timers and Serial Communications

Embedded Real-Time Systems Lecture: Timers and Serial Communications Dimitris Metafas, Ph. D.

1. Software and I/O devices

Software and I/O devices n Two ways of addressing I/O devices from the CPU n Memory mapped. I/O n n n Devices are mapped in memory address space, e. g. , the 7 segment LED Standard load and store instruction can manipulate devices Port mapped I/O n n Devices are not kept in memory address space Special processor instructions request data from devices n n n Example IN REG, PORT OUT REG, PORT Memory mapped. I/O uses the same load/store paradigm, but costs some of the address space Full address space is available for port mapped I/O, but requires extra instructions and control signals from the CPU 3

Access I/O devices n Writing assembly code to access devices can be cumbersome LDR MOV STRB n Use “EQU” assembler directive BASE LDR n R 0, =0 x 20200000 R 1, #0 x 0 C R 1, [R 0] EQU 0 x 20200000 R 0, =BASE Can also access devices using C programs C pointers can be used to write to a specific memory location unsigned char *ptr; ptr = (unsigned char *) 0 x 20200000; *ptr = (unsigned char) 0 x 0 C; n 4

I/O registers basics n I/O Registers are NOT like normal memory n n Device events can change their values (e. g. , status registers) Some are read only(e. g. , receive registers) Some are write only(e. g. , transmit registers) Sometimes multiple I/O registers are mapped to same address n n n selection of one based on other info (e. g. , read vs. write or extra control bits) Cache must be disabled for memory mappedaddresses When polling I/O registers, should tell compiler that value can change on its own and therefore should not be stored in a register n volatile int *ptr; (or int volatile *ptr; ) 5

Volatile keyword void test() { int *ptr = (int *) 0 x 20200000; int val=0; do { val+=*ptr; } while(val <= 100); void test() { volatile int *ptr=(int *) 0 x 2020…; int val=0; do { val+=*ptr; } while(val <= 100); } } Initial value: r 1 contains 0 x 20200000 Initial value: r 2 contains 0 x 2020… Assume r 0 contains val 0 x 00 0 x 04 0 x 08 0 x 0 C 0 x 10 0 x 14 LDR MOV ADD CMP BLE MOV r 1, [r 1, #0]; r 0, #0; val=0 r 0, r 1, r 0; val+=*ptr r 0, #0 x 64; val >= 100? 0 x 08; jmp to 0 x 08 pc, r 14 0 x 00 0 x 04 0 x 08 0 x 0 C 0 x 10 0 x 14 6 MOV LDR ADD CMP BLE MOV r 0, #0 r 1, [r 2, #0] r 0, r 1, r 0, #0 x 64 0 x 04 pc, r 14

2. Timers

Timer Counter Register System Clock 0 x 1206 Reload on Zero ÷ Clock Divider 000000 Countdown Register Interrupt to Processor 8 I/O Control

X board system clocks n Two oscillators n n 50 MHz and 66. 6 MHz All clocks are derived from these 2 sources n n 80200 processor ~733 MHz Memory 100 MHz PCI and serial ports 33. 3 MHz Ethernet 25 MHz 9

Timers in X Board n n n The 80200 based X Board has two 32 bit timers 33. 3 MHz peripheral bus clock is the time base These timers can interrupt the processor n n n Interrupt will be held active until cleared by the processor Each timer consists of a down counter which reloads itself when it hits underflow Can be programmed for one shot operation (disables itself when it hits zero) 10

Uses of a timer n n n Pause Function: Suspends task for a specified amount of time One shot timer: Single one time only timeout Periodic timer: Multiple renewable timeouts Time slicing: Chunks of time to each task Watchdog timer: reset the processor in abnormal cases 11

X Board Timer Status/Control registers 12

X Board Timer Preload registers 13

X Board Timer Current Value registers 14

Example n n Suppose that I want a timer of 0. 1 ms. Calculation of the preload register’s value Convert 0. 1 ms into clock cycles n n n 0. 1 ms * 33. 33 MHz = 3333 clock cycles This means that 3333 counts need to elapse for a 0. 1 ms timer before an interrupt is generated to indicate underflow (going from the preload value to 0) 3333 counts can be accomplished by setting the preload register to 3332 (because the interrupt is not issued until underflow actually hits) 15

Timer def for the X board (brh. h) typedef unsigned long U 32; // Timer Struct Definition typedef struct timer_rec { volatile U 32 stat_cntrl; volatile U 32 preload; volatile U 32 value; } timer; // Timer A and Timer B (points to status control register for each timer) #define TIMERA 0 x 21000300 #define TIMERB 0 x 21000320 // Flags for the timers #define TMR_INT_CLEAR #define TMR_INT #define TMR_CONT_MODE #define TMR_ENABLE #define TMR_STOP (used to set the value of stat_cntrl) (0 x 00000200) (0 x 00000002) (0 x 00000001) (0 x 0000) 16

Initializing the timers #include “brh. h” : : { // Get handle to Timer A (for example) timer *timer_a = (timer *)TIMERA; // Now, you can use timer_a in all of your functions, e. g. , start_timer() 17

3. Interrupt I/O vs Polled I/O

Polled I/O n Polled I/O requires the CPU to ask a device if the device requires servicing n Software plans for polling the devices and is written to know when a device will be serviced 19

Interrupt I/O n Interrupt I/O allows the device to interrupt the processor, announcing that the device requires attention n This allows the CPU to ignore devices unless they request servicing (via interrupts) n Software cannot plan for an interrupt because interrupts can happen at any time therefore, software has no idea when an interrupt will occur 20

Masking of interrupts n Processors can be programmed to ignore interrupts We call this masking of interrupts n Different types of interrupts can be masked (IRQ vs. FIQ) n 21

Polling example: switches #define SWITCH_BASE 0 x 18200000 int main(int argc, char * argv[]) { volatile unsigned int *switch. Bank = (unsigned int *) SWITCH_BASE; unsigned int tmp. Switch. State; unsigned int prev. Switch. State; /* get the current state of the switches */ prev. Switch. State = *switch. Bank & 0 xff; while (1) { /* loop until a switch is pressed */ while (prev. Switch. State == (tmp. Switch. State = (*switch. Bank & 0 xff))) {}; } } /* end main() */ 22

Polling I/O vs Interrupt I/O n n Polling requires code to loop until device is ready n Consumes lots of CPU cycles n Can provide quick response (guaranteed delay) Interrupts don't require code to loop until the device is ready n Device interrupts processor when it needs attention n Code can go off and do other things n Interrupts can happen at any time (Requires careful coding) 23

4. Serial Communications

Why serial communication ? n Serial communication is a pin efficient way of sending and receiving bits of data n n Sends and receives data one bit at a time over one wire While it takes eight times as long to transfer each byte of data this way (as compared to parallel communication), only a few wires are required Typically one to send, one to receive (for full duplex), and a common signal ground wire Simplistic way to visualize serial port n n Two 8 bit shift registers connected together Output of one shift register (transmitter) connected to the input of the other shift register (receiver) Common clock so that as a bit exits the transmitting shift register, the bit enters the receiving shift register Data rate depends on clock frequency 25

Serial communications n Communications over serial line Data is converted from parallel (bytes) to serial (bits) and bits are sent over wire (TX) n Receiving end (RX) translates bit stream back into parallel data (bytes) n 26

Modulation n When sending data over serial lines, logic signals are converted into a form the physical media (wires) can support n A Universal Asynchronous Receiver-Transmitter (UART) is used for n n n serial communications The UART generates signals with the same timing as the RS 232 standard used by the Personal Computer’s COM ports. The UART input/output uses 0 V for logic 0 and 5 V for logic 1. The RS 232 standard (and the COM port) use +12 V for logic 0 and – 12 V for logic 1. 27

Protecting Against Data Loss n How can data be lost? n n n Most serial ports use FIFO buffers so that data is not lost n n If the transmitter starts to send the next byte before the receiver has had a chance to process/read the current byte If the next byte is loaded at the transmitter end before the current byte has been completely transmitted Buffering of received bytes at receiver end for later processing Buffering of loaded bytes at transmitter end for later transmission Shift registers free to transmit and receive data without worrying about data loss The size of the FIFO buffers matter 28

Serial Port Rx. Register 0 1 2 3 4 5 6 7 FIFO Buffer 0 1 2 3 4 5 6 7 Clock 0 1 2 3 4 5 6 7 FIFO Buffer Tx. Register 0 1 2 3 4 5 6 7 Rx. Register FIFO Buffer 0 1 2 3 4 5 6 7 Processor Tx. Register 29 0 1 2 3 4 5 6 7 Peripheral

Protocols n n A Communications protocol is a convention for data transmission that includes such functions as timing, formatting and data representation Synchronous communication n Data transmitted as a steady stream at regular intervals n n All transmitted bits are synchronized to a common clock signal The two devices initially synchronize themselves to each other, and then continually send characters to stay synchronized Faster data transfer rates than asynchronous methods, because it does not require additional bits to mark the beginning and end of each data byte Asynchronous communication n n Data transmitted intermittently at irregular intervals Each device uses its own internal clock resulting in bytes that are transferred at arbitrary times Instead of using time as a way to synchronize the bits, the data format is used Data transmission is synchronized using the start bit of the word, while one or more stop bits indicate the end of the word n Asynchronous communications slightly slower than synchronous 30

Asynchronous Protocols n n n Many different types of electrical connection standards Timing is the same n idle line is assumed to be in high (1) state n each character begins with a zero (0) bit, followed by 8 data bits and then 1, 1 1/2, or 2 closing 1 bits. n Bits are usually encoded using ASCII Start (stop) bits identify the beginning (end) of each character also permits receiver to resynchronize local clock to each new character (characters can begin at arbitrary times) 31

Asynchronous Protocols n Bit Sampling n Receiver's clock is not identical to the transmitter's clock n Best if the sample is near the middle of a bit ( not always possible because of clock differences) n Receiver clock (in relation to transmitter) cannot gain or lose more than 1/2 bit per 10 to 11 clock periods (time to transmit one character) (Clocks must be accurate to within 5%) n Most receivers use a fast clock to determine the “middle” of a bit n Typical is 16 X clock which can take 16 samples per 1 bit n Begins by detecting start bit which clears clock counter n Clock counter increments to 16 for each tick of the receiver clock n When the counter reaches 8, it has reached the middle of the bit and takes the sample 32

Error detection n n n A single bit determined by the number of 1's in a word The simplest form of error detection Parity bit is appended to each group of bits (byte, word) Odd parity n Parity bit is chosen to force the number of 1's to be odd n Example: 0 0 0 0 1 0 1 0 1 Even parity n Parity bit is chosen to force the number of 1's to be even When receiving data, the receiver will check every group of bits n Parity checker determines if the parity of a group of bits is correct n If wrong, an error (exception) will be raised to let the processor and software know an error has occurred in parity bit 33

Interfacing Serial Data to Microprocessor n n n Processor has parallel buses for data need to convert serial data to parallel (and vice versa) Standard way is with UART Universal asynchronous receiver and transmitter 34

Interfacing Serial Data to Microprocessor Chip Reg Select R/W Control Tx Clock Tx Data Reg IRQ Tx Shift Reg Status Reg D 0 -D 7 Data Bus Buffers Tx Data CTS Control Reg Rx Data Reg Rx Shift Reg Rx Clock 35 RTS Rx Data

Serial bytes Serial ports on IBM style PCs support asynchronous communication only A “serial byte” usually consists of n n n Characters: 5 8 data bits Framing bits: 1 start bit, 1 parity bit (optional), 1 2 stop bits When serial data is stored on your computer, framing bits are removed, and this looks like a real 8 bit byte MSB n LSB 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 Specified as number of data bits parity type number of stop bits n n 8 N 1 a eight data bits, no parity bit, and one stop bit 7 E 2 a seven data bits, even parity, and two stop bits 36