Electronics Integration Status AHCAL Mathias Reinecke for the

Electronics Integration – Status AHCAL Mathias Reinecke for the AHCAL developers Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 1

Next prototype: Architecture the future … 1 st EUDET Prototype (1 st step) Commercial DIF, new mezzan. (CALIB, POWER), 1 HBU (later: 6) Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 2

Prototype Tiles Prototype Tile for HBU 0 dimensions in (mm; mm) Si. PM (0; 15) Mechanics Tile for HBU 0 (30; 30) Mirror (0; 0) WLS Alignment Pins (22. 5; 7. 5) (7. 5; 22. 5) Cutout (~8 mm) for cassette construction (done by „drilling“) 100 -150 prototype tiles (structures machined, not moulded): Problems with Si. PM assembly, impact on time schedule for HBU 0!! Tile‘s dimensions are fixed now! (=>HBU) Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 3

Tiles for EUDET module Standard Tile (moulded) (30; 30) Si. PM (0; 15) Mirror (0; 0) (mm; mm) WLS Alignment Pins (7. 5; 22. 5) (22. 5; 22. 5) Shorted (by 1 cm) tile for inter-layer sizes No time schedule up to now. Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 4

HCAL Base Unit (HBU 0) Cassette fixation Mechanics Tile Temp. Sensor SPIROC 1 Debug Conn. Signal IN Flexlead Conn. Power IN Two signal paths SPIROC 2 Prototype Tile Calibration Electr. (LED + Charge Inj) Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 5

HBU 0 Status -Integration concept fixed -Critical parts (connectors) ordered. -Layout is complex (1 -2 months), PCB manufacturing and assembly: 1 -2 months => realization in 2008 critical! - Schematic finished. Layout starts now! HBU schematic top layer Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 6

HBU Interconnection (Flexleads) Rigid (FR 4) -Two types of Flexleads (for Signals, Power) have been designed (CAD) Flexible (polyimide) Connector (0. 8 mm) -Flexleads allow +/-100µm displacement of connecting modules -Magnet-field tests up to a few Tesla done: no problems seen. -Flexleads can be ordered now! Done! Mathias Reinecke Flexlead CAD Layout Flexlead Structure EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 7

DIF Status -Based on commercial FPGA (Spartan 3 -1500) board -Command list and DIF state diagram in preparation -VHDL code generation soon (prototype firmware for USB access in 2008) Firmware status of ECAL/DHCAL? Reference documents for LDA-DIF interface (also: DAQ group)? Firmware development needs closer coordination. Mathias Reinecke DIF command list DIF state diagram EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 8

CALIB Status „AHCAL Calibration System“ (UV-LED and Charge Injection) -Concept fixed, schematic finished -µController software dev. ongoing (good progress) -Layout (CAD) starts now, expected to be finished: End of September. By M. Zeribi -Module should be available: November/December 08 Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 9

POWER Status „AHCAL Slab Power Regulators“ -Regulator setup fixed, schematic finished -Suitable for ILC-like power cycling -Layout and Production probably in 2009 (module can be replaced initially by bench-top power supplies) By H. Wentzlaff Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 10

AHCAL Slab Interface (Mech. ) HBU PCB Steel absorber HBU Flexlead Light-seal interconnection Robust interface Component height connector 2 cm Preliminary! 10 cm Cooling pipe Si. PM Tile Not in scale!! Mathias Reinecke Cassette bottom plate, extended Interface Board (IB) EUDET Annual Meeting 2008 – NIKHEF HCAL Endcap Board (HEB), with DIF 6. 10. 2008 11

DAQ – Data Rates (Testbeam) New tool available (Vincent Boudry) to calculate CALICE DAQ data rates and readout times for the run modes: - calibration/noise/physics – single event (e. g. ext trigger) - calibration/noise/physics – burst (internal trigger) - testbeam – single event* (e. g. external trigger? ) - testbeam – burst* (e. g. internal trigger) *Occupancy needed to estimate the amount of data. Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 12

AHCAL – Occupancy in testbeam Calculation and Results by B. Lutz (many thanks!!) • subdivided each layer into 21 sections • each section corresponds to one virtual chip (36 channels with 3 x 3 cm cells) • 798 total virtual chips (38 layers) • 80 Ge. V p+ beam hitting centrally • counting active chips per event Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 13

AHCAL – Total Number of ASICS hit • typically 200 / 798 = ¼ of the chips in 1 m 3 are hit Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 14

AHCAL – Active ASICs per layer active. Region: 36 tiles (1 virtual ASIC) Up to 12 ASICs carry data for a single testbeam event per layer. => use this number to estimate DAQ data rate! Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 15

Mechanics Status Next HBU 0 cross section CALIB DIF - Mechanical proposal (cassette, interface to DIF) has been set up for the AHCAL prototype (HBU 0, DIF as commercial board). -The necessary mechanical parts are currently designed within CAD tool => production within 2008 Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 16

Conclusions -AHCAL technical prototype (TP) does not cover a full slab, but ~150 channels (2 HBU 0 s, tile-prototypes). -Eudet module (detector layer) requires HBU redesign. A full slab (and detector layer) is expected for summer/autumn 2009. -timeline for TP is defined by HBU 0. -development of the modules CALIB and DIF (firmware) in 2008 possible. Mathias Reinecke EUDET Annual Meeting 2008 – NIKHEF 6. 10. 2008 17