Electronics for the Eu XFEL Clock and Control
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Electronics for the Eu. XFEL Clock and Control System Poster Number 104 Topical Workshop Department of Physics and Astronomy, University College London on Electronics for Erdem Motuk <emotuk@hep. ucl. ac. uk>, Martin Postranecky <mp@hep. ucl. ac. uk>, Matthew Warren <warren@hep. ucl. ac. uk>, Matthew Wing <mw@hep. ucl. ac. uk> Particle Physics ( TWEPP-2011 ) Vienna, Austria 26 to 30 Sept. 2011 Design and Development of Electronics for the Eu. XFEL Clock and Control System • Clock and Control ( CC ) hardware and firmware designed for the Eu. XFEL DAQ system Red LED – FPGA Prog. • The system exploits the data handling advances provided by the new telecommunication architecture standard for physics • The CC is responsible for synchronising the DAQ system to overall system timing Prog. FPGA Switch Xilinx PROM GSI 18 x 4 Mb SRAM Ext. 5 V/3 A Conn. Spartan 3 E FPGA VME Base Address A<31 -28> A<27 -24> VME J 1 Clock MUX/PLL VME J 2 • The hardware consists of a DESY designed MTCA. 4 board and a UCL designed Rear Transition Module ( RTM ) • Each RTM controls up to 16 Front End Modules ( FEMs ) for a 1 Megapixel 2 D detector 80. 15733 MHz XTAL Osc. • The CC system is designed to provide extendibility and scalability to support future upgrades to the DAQ or larger detectors Red LED 3 x Supply OK 40 -pin DIL BREAK-OUT HEADER (incl. 3 x LEDs 3 12 x LEDs 4 x diff. pairs 2 V 5 LVDS ) 32 3 SHIFT 3 2 6 x FUSES 2 REG. 3 3 Buffers Xilinx Spartan 3 e XC 3 S 1600 E-5 FGG 400 C VME BASE ADDRESS A<31 -24> 8 FPGA & PROM SW SW CLKIN 1 2 NIM ECL NIM 8 IN 4 20 x LEMO-00 Clk+4 Delay Lines VME MPX CLKIN select 8 PLL 40/80 MHz select TTL IN 6 CLKOUT 0 CLKOUT 1 2 7 x Supply Monitor 2 IN 0 IN 2 Blue LED 4 x Supply OK J 2 CLK Master DELAY 4 4 4 x Slave DELAYS 4 2 8 OUT 4 2 x LEDs 80. 15733 MHz 8 2 TTL OUT 6 22 8 16 ( incl. 2 x diff. pairs 2 V 5 LVDS ) 40 -pin DIL HEADER SER<7 -4> All POWER Monitor 16 8 Set Serial No. 7 X-TAL 16 -pin AUX. CONNECTOR J 1 7 OUT 0 NIM VME : 2 NIM ECL OUT 2 Buffers CLKIN 0 6 x POWER 2 x GND pins Data 4 Mbx 18 SRAM Address 7 +5 V +3 V 3 +2 V 5 +1 V 8 +1 V 2 -5 V -2 V 16 SER<3 -0> DIL JTAG for USB MCU 6 x DC-DC MOD. RECORD 6 8 J-TAG HEX SELECT FUSES SW SHIFT REG. 4 SERIAL NO. 8 4 USB SW USB MCU 24 SW EXT. +5 V IN SW MP-UCL, 18 August 2011 • The CC system consists of a MTCA. 4 Advanced Mezzanine Card ( AMC ) board and a Rear Transition Module ( RTM ) Set Mod. Record USB Reset Switch MR<7 -4> MR<3 -0> • The MTCA. 4 AMC board ( DAMC 2 ) is designed by DESY as a multipurpose FPGA hardware platform for various projects in DESY and provides the processing capability for the CC functionality. We have developed a custom RTM board according to the MTCA. 4 standard which connects to the DAMC 2 through two thirty-pair Advanced Differential Fabric ( ADF ) connectors • The connections to the FEM boards are realised on AC-coupled LVDS links on CAT 5 RJ 45 cables. The RTM board provides the number of channels to support up to 16 FEM modules for a 1 MPixel 2 D detector. CLK-IN<1 -0> ECL/NIM Sel. IN<7 -0> TTL/NIM Sel. CLK-OUT<1 -0> ECL/NIM Sel. OUT<7 -0> TTL/NIM Sel. SIL JTAG for FPGA • Each channel comprises 4 LVDS pairs on an RJ 45 connector : - Output clock ( FAST clock ) : ~99 MHz clock derived from the 4. 5 MHz bunch clock. - Output data ( FAST data ) : trigger start signal and train ID data - Veto : bunch reject data encoded on a either 99 or 4. 5 MHz clock - Status : status feedback from the FEMs • Need to design, develop and test receiver circuitry required for ACcoupling of the data signal on the FEMs and the status signal on the CCs Ext. +5 V / 3 A Power Conn. VME J 2 VME J 1 40 -pin DIL HEADER USB MCU JTAG Programm. Reset Switch 3 x STATUS LEDs ( 3 x 4 LEDs Programmable ) ( Programm. ) Global Reset Switch ( FPGA, MCU ) DATA-IN<7 -0> 8 x LEMOs 00 CLK-IN<1 -0> 2 x LEMOs 00 Prog. MODE Hex Switch. DATA-OUT<7 -0> 8 x LEMOs 00 CLK-OUT<1 -0> 2 x LEMOs 00 AUX. DIL 16 x I/Os FPGA JTAG 4 -pin USB