ELEC 7770 Advanced VLSI Design Spring 2008 Fault
![ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J. ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J.](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-1.jpg)
![Fault Simulation § Problem and motivation § Fault simulation algorithms § Serial § Parallel Fault Simulation § Problem and motivation § Fault simulation algorithms § Serial § Parallel](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-2.jpg)
![Problem and Motivation § Fault simulation Problem: Given § A circuit § A sequence Problem and Motivation § Fault simulation Problem: Given § A circuit § A sequence](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-3.jpg)
![Fault Simulator in VLSI Design Verified design netlist Verification input stimuli Fault simulator Test Fault Simulator in VLSI Design Verified design netlist Verification input stimuli Fault simulator Test](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-4.jpg)
![Fault Simulation Scenario § Circuit model: mixed-level § Mostly logic with some switch-level for Fault Simulation Scenario § Circuit model: mixed-level § Mostly logic with some switch-level for](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-5.jpg)
![Fault Simulation Scenario (Cont. ) § Faults: § Mostly single stuck-at faults § Sometimes Fault Simulation Scenario (Cont. ) § Faults: § Mostly single stuck-at faults § Sometimes](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-6.jpg)
![Fault Simulation Algorithms § Serial § Parallel § Deductive § Concurrent § Differential* * Fault Simulation Algorithms § Serial § Parallel § Deductive § Concurrent § Differential* *](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-7.jpg)
![Serial Algorithm § Algorithm: Simulate fault-free circuit and save responses. § Repeat following steps Serial Algorithm § Algorithm: Simulate fault-free circuit and save responses. § Repeat following steps](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-8.jpg)
![Serial Algorithm (Cont. ) § Disadvantage: Much repeated computation; CPU § time prohibitive for Serial Algorithm (Cont. ) § Disadvantage: Much repeated computation; CPU § time prohibitive for](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-9.jpg)
![Parallel Fault Simulation § Compiled-code method; best with two-states (0, 1) § Exploits inherent Parallel Fault Simulation § Compiled-code method; best with two-states (0, 1) § Exploits inherent](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-10.jpg)
![Parallel Fault Simulation Example Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Parallel Fault Simulation Example Bit 0: fault-free circuit Bit 1: circuit with c s-a-0](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-11.jpg)
![Deductive Fault Simulation § One-pass simulation § Each line k contains a list Lk Deductive Fault Simulation § One-pass simulation § Each line k contains a list Lk](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-12.jpg)
![Deductive Fault Sim. Example Notation: Lk is fault list for line k kn is Deductive Fault Sim. Example Notation: Lk is fault list for line k kn is](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-13.jpg)
![Concurrent Fault Simulation § Event-driven simulation of fault-free circuit and only those § § Concurrent Fault Simulation § Event-driven simulation of fault-free circuit and only those § §](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-14.jpg)
![Concurrent Fault Sim. Example a 0 0 1 a b 1 1 1 c Concurrent Fault Sim. Example a 0 0 1 a b 1 1 1 c](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-15.jpg)
![Fault Sampling § A randomly selected subset (sample) of faults is § § § Fault Sampling § A randomly selected subset (sample) of faults is § § §](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-16.jpg)
![Motivation for Sampling § Complexity of fault simulation depends on: § § Number of Motivation for Sampling § Complexity of fault simulation depends on: § § Number of](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-17.jpg)
![Random Sampling Model Detected fault All faults with a fixed but unknown coverage Random Random Sampling Model Detected fault All faults with a fixed but unknown coverage Random](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-18.jpg)
![Probability Density of Sample Coverage, c 1 p (x) = Prob (x ≤ c Probability Density of Sample Coverage, c 1 p (x) = Prob (x ≤ c](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-19.jpg)
![Sampling Error Bounds C (1 - C ) | x - C | = Sampling Error Bounds C (1 - C ) | x - C | =](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-20.jpg)
![Summary § Fault simulator is an essential tool for test development. § Concurrent fault Summary § Fault simulator is an essential tool for test development. § Concurrent fault](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-21.jpg)
![Exercise § For the circuit shown above § Using the parallel fault simulation algorithm, Exercise § For the circuit shown above § Using the parallel fault simulation algorithm,](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-22.jpg)
![Exercise Answer Parallel fault simulation of four PI faults is illustrated below. Fault PI Exercise Answer Parallel fault simulation of four PI faults is illustrated below. Fault PI](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-23.jpg)
- Slides: 23
![ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D Agrawal James J ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J.](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-1.jpg)
ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng. auburn. edu http: //www. eng. auburn. edu/~vagrawal/COURSE/E 7770_Spr 08/course. html Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1
![Fault Simulation Problem and motivation Fault simulation algorithms Serial Parallel Fault Simulation § Problem and motivation § Fault simulation algorithms § Serial § Parallel](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-2.jpg)
Fault Simulation § Problem and motivation § Fault simulation algorithms § Serial § Parallel § Deductive § Concurrent § Random Fault Sampling § Summary § Review problems Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 2
![Problem and Motivation Fault simulation Problem Given A circuit A sequence Problem and Motivation § Fault simulation Problem: Given § A circuit § A sequence](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-3.jpg)
Problem and Motivation § Fault simulation Problem: Given § A circuit § A sequence of test vectors § A fault model Determine § Fault coverage - fraction (or percentage) of modeled faults detected by test vectors § Set of undetected faults § Motivation § Determine test quality and in turn product quality § Find undetected fault targets to improve tests Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 3
![Fault Simulator in VLSI Design Verified design netlist Verification input stimuli Fault simulator Test Fault Simulator in VLSI Design Verified design netlist Verification input stimuli Fault simulator Test](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-4.jpg)
Fault Simulator in VLSI Design Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled fault list Remove tested faults Fault coverage ? Low Test generator Test compactor Delete vectors Add vectors Adequate Stop Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 4
![Fault Simulation Scenario Circuit model mixedlevel Mostly logic with some switchlevel for Fault Simulation Scenario § Circuit model: mixed-level § Mostly logic with some switch-level for](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-5.jpg)
Fault Simulation Scenario § Circuit model: mixed-level § Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals § High-level models (memory, etc. ) with pin faults § Signal states: logic § Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits § Four states (0, 1, X, Z) for sequential MOS circuits § Timing: § Zero-delay for combinational and synchronous circuits § Mostly unit-delay for circuits with feedback Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 5
![Fault Simulation Scenario Cont Faults Mostly single stuckat faults Sometimes Fault Simulation Scenario (Cont. ) § Faults: § Mostly single stuck-at faults § Sometimes](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-6.jpg)
Fault Simulation Scenario (Cont. ) § Faults: § Mostly single stuck-at faults § Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use § Equivalence fault collapsing of single stuck-at faults § Fault-dropping – a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis § Fault sampling – a random sample of faults is simulated when the circuit is large Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 6
![Fault Simulation Algorithms Serial Parallel Deductive Concurrent Differential Fault Simulation Algorithms § Serial § Parallel § Deductive § Concurrent § Differential* *](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-7.jpg)
Fault Simulation Algorithms § Serial § Parallel § Deductive § Concurrent § Differential* * See M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 5. Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 7
![Serial Algorithm Algorithm Simulate faultfree circuit and save responses Repeat following steps Serial Algorithm § Algorithm: Simulate fault-free circuit and save responses. § Repeat following steps](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-8.jpg)
Serial Algorithm § Algorithm: Simulate fault-free circuit and save responses. § Repeat following steps for each fault in the fault list: § Modify netlist by injecting one fault § Simulate modified netlist, vector by vector, comparing responses with saved responses § If response differs, report fault detection and suspend simulation of remaining vectors Advantages: § Easy to implement; needs only a true-value simulator, less memory § Most faults, including analog faults, can be simulated Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 8
![Serial Algorithm Cont Disadvantage Much repeated computation CPU time prohibitive for Serial Algorithm (Cont. ) § Disadvantage: Much repeated computation; CPU § time prohibitive for](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-9.jpg)
Serial Algorithm (Cont. ) § Disadvantage: Much repeated computation; CPU § time prohibitive for VLSI circuits Alternative: Simulate many faults together Test vectors Fault-free circuit Comparator f 1 detected? Comparator f 2 detected? Comparator fn detected? Circuit with fault f 1 Circuit with fault f 2 Circuit with fault fn Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 9
![Parallel Fault Simulation Compiledcode method best with twostates 0 1 Exploits inherent Parallel Fault Simulation § Compiled-code method; best with two-states (0, 1) § Exploits inherent](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-10.jpg)
Parallel Fault Simulation § Compiled-code method; best with two-states (0, 1) § Exploits inherent bit-parallelism of logic operations § § on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length Speed up over serial method ~ w-1 Not suitable for circuits with timing-critical and non. Boolean logic Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 10
![Parallel Fault Simulation Example Bit 0 faultfree circuit Bit 1 circuit with c sa0 Parallel Fault Simulation Example Bit 0: fault-free circuit Bit 1: circuit with c s-a-0](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-11.jpg)
Parallel Fault Simulation Example Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1 1 c s-a-0 detected 1 0 1 a 1 1 1 b 1 0 1 c s-a-0 e 1 0 1 g 0 0 0 d Spring 08, Mar 27 f s-a-1 0 0 1 ELEC 7770: Advanced VLSI Design (Agrawal) 11
![Deductive Fault Simulation Onepass simulation Each line k contains a list Lk Deductive Fault Simulation § One-pass simulation § Each line k contains a list Lk](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-12.jpg)
Deductive Fault Simulation § One-pass simulation § Each line k contains a list Lk of faults detectable on it § Following true-value simulation of each vector, fault lists of § § all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists PO fault lists provide detection data Limitations: § Set-theoretic rules difficult to derive for non-Boolean gates § Gate delays are difficult to use Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 12
![Deductive Fault Sim Example Notation Lk is fault list for line k kn is Deductive Fault Sim. Example Notation: Lk is fault list for line k kn is](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-13.jpg)
Deductive Fault Sim. Example Notation: Lk is fault list for line k kn is s-a-n fault on line k b 1 {b 0} {a 0} {b 0 , c 0} c d {b 0 , d 0} Spring 08, Mar 27 = {a 0 , b 0 , c 0 , e 0} e f 1 0 {b 0 , d 0 , f 1} ELEC 7770: Advanced VLSI Design (Agrawal) 1 g U a 11 Lg = (Le Lf ) U {g 0} = {a 0 , c 0 , e 0 , g 0} Faults detected by the input vector 13
![Concurrent Fault Simulation Eventdriven simulation of faultfree circuit and only those Concurrent Fault Simulation § Event-driven simulation of fault-free circuit and only those § §](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-14.jpg)
Concurrent Fault Simulation § Event-driven simulation of fault-free circuit and only those § § parts of the faulty circuit that differ in signal states from the fault-free circuit. A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are implicitly simulated. Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility. ) Faster than other methods, but uses most memory. Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 14
![Concurrent Fault Sim Example a 0 0 1 a b 1 1 1 c Concurrent Fault Sim. Example a 0 0 1 a b 1 1 1 c](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-15.jpg)
Concurrent Fault Sim. Example a 0 0 1 a b 1 1 1 c d 1 0 c 0 1 0 0 e 0 1 1 e 1 0 0 10 b 0 01 Spring 08, Mar 27 b 0 1 0 0 f d 0 01 1 0 0 f 1 11 1 a 0 g 0 1 0 0 g ELEC 7770: Advanced VLSI Design (Agrawal) 0 b 0 0 0 1 1 f 1 c 0 0 e 0 0 1 1 1 d 0 15
![Fault Sampling A randomly selected subset sample of faults is Fault Sampling § A randomly selected subset (sample) of faults is § § §](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-16.jpg)
Fault Sampling § A randomly selected subset (sample) of faults is § § § simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory. ) Disadvantage: Limited data on undetected faults. Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 16
![Motivation for Sampling Complexity of fault simulation depends on Number of Motivation for Sampling § Complexity of fault simulation depends on: § § Number of](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-17.jpg)
Motivation for Sampling § Complexity of fault simulation depends on: § § Number of gates § Number of faults § Number of vectors Complexity of fault simulation with fault sampling depends on: § Number of gates § Number of vectors Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 17
![Random Sampling Model Detected fault All faults with a fixed but unknown coverage Random Random Sampling Model Detected fault All faults with a fixed but unknown coverage Random](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-18.jpg)
Random Sampling Model Detected fault All faults with a fixed but unknown coverage Random picking Np = total number of faults Ns = sample size Ns << Np (population size) C = fault coverage (unknown) Spring 08, Mar 27 Undetected fault c = sample coverage (a random variable) ELEC 7770: Advanced VLSI Design (Agrawal) 18
![Probability Density of Sample Coverage c 1 p x Prob x c Probability Density of Sample Coverage, c 1 p (x) = Prob (x ≤ c](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-19.jpg)
Probability Density of Sample Coverage, c 1 p (x) = Prob (x ≤ c ≤ x +dx ) = ─────── e σ (2 π) 1/2 C (1 - C) Variance, σ = ────── Ns (x – C )2 - ───── 2σ 2 p (x) 2 σ σ Mean = C C -3σ x C Sample coverage Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) Sampling error C +3σ 1. 0 x 19
![Sampling Error Bounds C 1 C x C Sampling Error Bounds C (1 - C ) | x - C | =](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-20.jpg)
Sampling Error Bounds C (1 - C ) | x - C | = 3 [ ────── ] 1/2 Ns Solving the quadratic equation for C, we get the 3 -sigma (99. 7% confidence) estimate: 4. 5 C 3σ = x ± ── [1 + 0. 44 Ns x (1 - x )]1/2 Ns Where Ns is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39, 096 faults has an actual fault coverage of 87. 1%. The measured coverage in a random sample of 1, 000 faults is 88. 7%. The above formula gives an estimate of 88. 7% ± 3%. CPU time for sample simulation was about 10% of that for all faults. Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 20
![Summary Fault simulator is an essential tool for test development Concurrent fault Summary § Fault simulator is an essential tool for test development. § Concurrent fault](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-21.jpg)
Summary § Fault simulator is an essential tool for test development. § Concurrent fault simulation algorithm offers the best choice. § For restricted class of circuits (combinational and § synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency. For large circuits, the accuracy of random fault sampling only depends on the sample size (1, 000 to 2, 000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator. Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 21
![Exercise For the circuit shown above Using the parallel fault simulation algorithm Exercise § For the circuit shown above § Using the parallel fault simulation algorithm,](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-22.jpg)
Exercise § For the circuit shown above § Using the parallel fault simulation algorithm, determine which of the four primary input faults are detectable by the test 00. Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 22
![Exercise Answer Parallel fault simulation of four PI faults is illustrated below Fault PI Exercise Answer Parallel fault simulation of four PI faults is illustrated below. Fault PI](https://slidetodoc.com/presentation_image_h2/0d60e1f0e1fd77dbfc15f8e0221571ac/image-23.jpg)
Exercise Answer Parallel fault simulation of four PI faults is illustrated below. Fault PI 2 s-a-1 is detected by the 00 test input. 00100 00001 PI 2=0 No fault PI 1 s-a-0 PI 1 s-a-1 PI 2 s-a-0 PI 2 s-a-1 00001 Spring 08, Mar 27 00001 ELEC 7770: Advanced VLSI Design (Agrawal) PI 2 s-a-1 detected PI 1=0 23
Rotary district 7770
Fault coverage in vlsi
Manufacturing test principles in vlsi
2008 2008
Elec 4601
Elec4601
Elec service plus
Picture recognition
Elec
Elec
Elec
Superposition electric circuits
Spring, summer, fall, winter... and spring cast
Winter spring summer or fall
Memory design in vlsi
Vlsi design flow y chart
Biucache
Subsystem design in vlsi
Mixed signal vlsi design
Rom design in vlsi
Intro to vlsi
Y chart in vlsi design
Cmos design rules
Modularity in vlsi design means