ELEC 52706270 Spring 2013 LowPower Design of Electronic

ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Test Power Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng. auburn. edu http: //www. eng. auburn. edu/~vagrawal/COURSE/E 6270_Spr 13/course. html Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 1

Power Considerations in Design l l A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function. Power buses are laid out to carry the maximum current necessary for the function. Heat dissipation of package conforms to the average power consumption during the intended function. Layout design and verification must account for “hot spots” and “voltage droop” – delay, coupling noise, weak signals. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 2

Testing Differs from Functional Operation Other chips System inputs System outputs VLSI chip system Functional inputs Copyright Agrawal, 2007 Functional outputs ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 3

Basic Mode of Testing Packaged or unpackaged device under test (DUT) DUT output for comparison with expected response stored in ATE VLSI chip Test vectors: Pre-generated and stored in ATE Copyright Agrawal, 2007 Clock Power Automatic Test Equipment (ATE): Control processor, vector memory, timing generators, power module, response comparator ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 4

Functional Inputs vs. Test Vectors l Functional inputs: Functionally meaningful signals l Generated by circuitry l l Restricted set of inputs l May have been optimized to reduce logic activity and power Copyright Agrawal, 2007 l Test vectors: Functionally irrelevant signals l Generated by software to test modeled faults l Can be random or pseudorandom l May be optimized to reduce test time; can have high logic activity l May use testability logic for test application l ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 5

An Example VLSI chip in system operation 3 -bit random vectors Binary to decimal converter 8 -bit 1 -hot VLSI chip vectors system VLSI chip under test High activity 8 -bit test vectors from ATE Copyright Agrawal, 2007 VLSI chip ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 6

Comb. Circuit Power Optimization Given a set of test vectors l Reorder vectors to minimize the number of transitions at primary inputs l 0101 0011 00001111 11 transitions Combinational circuit (tested by exhaustive vectors) 01111000 Rearranged vector set 0011 00011110 Copyright Agrawal, 2007 produces 7 transitions ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 7

Reducing Comb. Test Power Original tests: V 1 V 2 V 3 V 4 V 5 1 1 0 0 0 1 0 1 0 1 1 1 10 input transitions Reordered tests: V 1 V 3 V 5 V 4 V 2 1 0 0 0 1 1 1 0 0 1 1 0 5 input transitions Copyright Agrawal, 2007 1 V 1 3 3 2 V 4 4 V 2 2 1 3 V 3 1 V 5 2 Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once. But, we need an open loop solution. ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 8

Open-Loop TSP 1 0 3 V 1 0 0 2 3 V 0 0 V 4 4 V 2 2 1 3 V 5 V 3 1 2 0 l l l Add a node V 0 at distance 0 from all other nodes. Solve TSP for the new graph. Delete V 0 from the solution. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 9

Combinational Vector Ordering l l l TSP has exponential complexity; good heuristics are available. For other extensions: l V. Dabholkar, S. Chakravarty, I Pomeranz and S. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application, ” IEEE Trans. CAD, vol. 17, no. 12, pp. 1325 -1333, Dec. 1998. Typical average power saving: l 30 -50% l 50 -60% with vector repetition (to satisfy peak power) l ? ? ? With inserted vectors (to satisfy peak power) Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 10

Traveling Salesperson Problem l l l A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, 1983. E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, 1984. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 11

Example: Branch and Bound Method l A combinational circuit is tested by a set of five vectors. The test system initializes to the first vector 0000, which should be retained as the starting vector. Remaining vectors can be arbitrarily sequenced. Find the minimum energy test sequence. How much does your sequence save over the original sequence? The given test vector sequence is: Vector number Copyright Agrawal, 2007 1 0 0 2 1 1 3 1 0 0 0 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 4 0 1 1 0 5 1 0 0 1 12

Begin with a Greedy Solution Designated start 1 2 4 2 5 2 2 1 4 4 Copyright Agrawal, 2007 1 2 3 3 3 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 13

Branch and Bound Search Slack = 6 1 Edge weight = 4 2 1 2 Slack = 2 2 3 3 2 4 3 2 5 3 2 Slack S = 0 =– 1 Terminate search when slack ≤ 0 Copyright Agrawal, 2007 5 4 1 3 4 5 4 4 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . All searches terminate before reaching leaf node. Minimum path length = 6 2 2 2 4 Greedy path Length = 6 14

C 6288: Test Vector Ordering Paul Wray, “Minimize Test Power for Benchmark Circuit c 6288 by Optimal Ordering of Vectors, ” Class Project, ELEC 5270, Spring 2009. Power. Point Presentation and Report: www. eng. auburn. edu/~vagrawal/COURSE/E 6270_Spr 09/course. html Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 15

Scan Testing Primary inputs Primary outputs Combinational logic Scan-out SO Scan enable SE Scan-in SI Copyright Agrawal, 2007 Scan flipflops D D SI 1 0 SO mux D’ DFF D’ SE ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 16

Some Properties of Scan Testing l Two modes of operation: l Normal mode l Scan mode l Three-step test application: l Scan-in: sets inputs of logic in scan mode. l Capture: captures logic outputs in normal mode. l Scan-out: observes captured outputs in scan mode. l Tests are non-functional; some tests may consume excess power and could have been intentionally avoided in functional mode. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 17

Example: State Machine Functional transitions Functional state transitions S 1 S 5 S 2 S 4 S 3 State encoding S 1 = 000 S 2 = 001 S 3 = 010 S 4 = 011 S 5 = 100 Copyright Agrawal, 2007 State transition Comb. State input changes/clock 000 → 010 1 000 → 100 1 001 → 011 1 010 → 001 2 011 → 000 2 100 → 011 3 (Peak) Av. transitions 1. 667 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 18

Reduced Power Design Functional transitions Functional state transitions S 5 S 4 S 1 S 2 S 3 Reduced power state encoding S 1 = 000 S 2 = 011 S 3 = 001 S 4 = 010 S 5 = 100 Copyright Agrawal, 2007 State transition Comb. State input changes/clock 000 → 001 1 000 → 100 1 011 → 010 1 001 → 011 1 010 → 000 1 100 → 010 2 (Peak) Av. transitions 1. 167 (– 30%) ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 19

Scan Testing: Shift-in, Shift-out Primary inputs Combinational logic Primary outputs Scan-out 100 FF=0 Scan-in 010 Shift-out transition FF=1 Shift-in transition Scan transitions Per clock State state transition changes 100 → 010 2 010 → 101 3 101 → 010 3 All transitions 8 Shift-in transitions = Σ (scan chain length – position of transition) Shift-out transitions = Σ (position of transition) Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 20

Scan Testing: Capture Primary inputs 1 0 Combinational logic FF=0 FF=1 FF=0 Copyright Agrawal, 2007 1 Primary 1 outputs 1 0 Capture transitions: 3 Note that 101 is not a functional state in the reduced power state encoding. 1 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 21

A Four Flip-Flop Example 010100 01000 10 transitions Combinational Logic Scanout F 4 0 F 3 0 F 2 0 F 1 0 0101 Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 22

Change Scan Chain Order 00000 11000 00000 10000 2 transitions Combinational Logic F 4 0 Scanout F 3 0 F 2 0 1100 Copyright Agrawal, 2007 F 1 0 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 23

0 1 1 Combinational Logic F 4 1 Output vector Input vector Capture Power 3 transitions Scanout F 3 0 F 2 1 Next vector states Copyright Agrawal, 2007 F 1 0 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 24

0 1 1 Combinational Logic F 4 1 Output vector Input vector Vector Order - Select Next Vector 3 transitions Scanout F 3 1 Next vector states 1111 or 1100 or 0011 Select 1100 Copyright Agrawal, 2007 F 2 0 Captured response F 1 1 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 25

Dynamic Power of Scan Test l Capture power can be reduced: l l A vector generation problem Shift-in and shift-out power is reduced by vector ordering and scan chain ordering l l l Construct a flip-flop node graph; edges weighted with shift in/shift out activity Find shortest distance Hamiltonian paths between all node pairs Select the path that minimizes shift power Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 26

Shift-in and Shift-out Matrices N Scan flip-flops: F 1 through FN; M vectors: V 1 through VM F 1 → F 2 · → · Fj· → ·Fk · → · FN F 1 → F 2 · → · F j · → · Fk · → · FN V 1 0 1 ··· 0 ··· 1 1 1 ··· 0 V 2 1 1 ··· 0 0 1 ··· 0 ··· ··· ··· Ij ··· VM 0 0 ··· ··· 1 ··· Ik ··· ··· 0 ··· 1 Oj 0 ··· ··· ··· Flip-flop states for test input 0 ··· ··· Ok ··· ··· 1 Test output states 27 Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . .

A Complete Graph wjk = Hamming(Ij, Ik) + Hamming(Oj, Ok) w 12 F 1 w 16 w 24 w 23 w 26 w 15 F 6 F 2 w 13 w 14 w 25 F 3 w 36 w 46 w 35 w 56 w 34 F 5 F 4 w 45 Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 28

Graph Solutions for Scan Power l l High complexity of Hamiltonian path finding requires use of heuristics. Average power saving: ~30 -50% logic, ~10 -20% flip-flops. Y. Bonhomme, P. Girard, Landrault, and S. C. Pravossoudovtich, “Power Driven Chaining of Flip-Flops in Scan Architectures, ” Proc. International Test Conf. , 2002, pp. 796– 803. Y. Bonhomne, P. Girard, L. Guiller, Landrault, and S. C. Pravossoudovtich, “Power-Driven Routing-Constrained Scan Chain Design, ” J. Electronic Testing: Theory and Applications, vol. 20, no. 6, pp. 647– 660, Dec. 2004. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 29

Low Power Scan Flip-Flop with Gated Data SO SO D’ SI DFF 1 mux SI SE CK D mux D 0 D’ DFF CK SE SFF: Scan FF cell Copyright Agrawal, 2007 SFF-GD: Gated data scan FF cell ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 30

Low Power Scan Flip-Flop with Gated Clock and Data SO SI 1 mux D 0 D’ DFF CK SE SFF-GCKD: Gated clock and data scan FF cell Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 31

s 5378: Normal Mode Operation 1, 000 random vectors l Clock period = 50 ns l Technology: TSMC 025 l FF cell No. of used gates Dynamic power (μW) Logic Glitch Dyn. Sh. Ck. Leak. (μW) Clock (μW) FF (μW) Total (μW) FF 2958 77. 9 17. 5 95. 4 14. 1 0. 129 220. 3 751. 6 1081. 5 SFF 3137 81. 8 19. 5 101. 3 13. 9 0. 130 220. 3 751. 7 1087. 3 SFFGD 3317 85. 1 19. 8 104. 9 15. 0 0. 132 220. 3 751. 7 1091. 9 SFFGCKD 3675 89. 9 56. 8 146. 7 23. 9 0. 136 118. 8 33. 2 322. 7 Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 32

s 5378: Scan Test Mentor Graphics Fastscan, 98. 9% coverage l Clock period = 50 ns l Technology: TSMC 025 l FF cell No. of used gates Dynamic power (μW) Logic Glitch Dyn. Sh. Ck. Leak. (μW) Clock (μW) FF (μW) Total (μW) SFF 3137 356. 8 60. 4 417. 2 26. 2 0. 146 220. 3 848. 5 1512. 4 SFFGD 3317 93. 5 33. 6 127. 2 7. 7 0. 150 220. 3 850. 7 1206. 0 SFFGCKD 3675 146. 8 241. 9 388. 7 61. 9 0. 154 118. 9 164. 1 733. 7 Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 33

Reference for Power Analysis l J. D. Alexander, Simulation Based Power Estimation For Digital CMOS Technologies, Master’s Thesis, Auburn University, Dept. of ECE, December 2008. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 34

Low Power Scan Flip-Flop Reducing Shift Power Scanin D Q FF 1 D Q FF 2 D Q FFN Scanout Scan Enable CLK Copyright Agrawal, 2007 Multi-phase clock generator ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 35

Built-In Self-Test (BIST) Linear feedback shift register (LFSR) Pseudo-random patterns BIST Controller Circuit under test (CUT) Circuit responses Multiple input signature register (MISR) Clock C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: Springer, 2002. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 36

Test Scheduling Example R 1 R 2 M 1 M 2 R 3 R 4 A datapath Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 37

BIST Configuration 1: Test Time M 1 MISR 1 LFSR 2 M 2 Test power LFSR 1 T 2: test for M 2 T 1: test for M 1 MISR 2 Test time Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 38

BIST Configuration 2: Test Power M 1 MISR 1 Copyright Agrawal, 2007 LFSR 2 M 2 Test power R 1 T 1: test for M 1 MISR 2 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . T 2: test for M 2 Test time 39

Testing of MCM and SOC Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e. g. , LFSR) or as output response analyzers (e. g. , MISR). l Test resources (R 1, . . . ) and tests (T 1, . . . ) are identified for the system to be tested. l Each test is characterized for test time, power dissipation and resources it requires. l Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 40

Resource Allocation Graph (A Bipartite Graph) T 1 R 2 Copyright Agrawal, 2007 T 2 R 3 T 3 R 4 T 4 R 5 T 5 R 6 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . R 7 T 6 R 8 R 9 41

Definition: Bipartite Graph l l A bipartite graph (or bigraph) is a graph whose vertices can be divided into two disjoint sets U and V such that every edge connects a vertex in U to one in V; that is, U and V are independent sets. Equivalently, a bipartite graph is a graph that does not contain any odd-length cycles. A bipartite graph has no clique of size 3 or larger. A bipartite graph can be colored with two colors (chromatic number = 2). Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 42

Test Compatibility Graph (TCG) T 1 (2, 100) T 6 (1, 100) T 2 (1, 10) T 5 (2, 10) T 3 (1, 10) Power Pmax = 4 Copyright Agrawal, 2007 Test time T 4 (1, 5) Tests that form a clique can be performed concurrently. ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 43

Definition: Clique l l l A clique is an undirected graph in which every vertex is connected to every other vertex. A clique is a complete graph. the maximum clique problem, is to find the largest clique in a graph. Finding whethere is a clique of a given size in a graph (the clique problem) is NP-complete. C. Bron and J. Kerbosch (1973): “Algorithm 457: Finding All Cliques of an Undirected Graph. , ” Communications of the ACM, vol. 16, no. 9. ACM Press: New York. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 44

A Similar Definition: SCC l l A directed graph is called strongly connected if there is a path from each vertex in the graph to every other vertex. Strongly connected components (SCC) of a directed graph are its maximal strongly connected subgraphs. If each strongly connected component is contracted to a single vertex, the resulting graph is a directed acyclic graph (DAG). T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. Introduction to Algorithms, Second Edition, MIT Press and Mc. Graw-Hill, 2001, ISBN 0262 -03293 -7. Finding SCCs, O(V+E) Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 45

Find All Cliques in TCG CLIQUE NO. i TEST NODES TEST LENGTH, Li POWER, Pi 1 T 1, T 3, T 5 100 5 2 T 1, T 3, T 4 100 4 3 T 1, T 6 100 3 4 T 1, T 5 100 4 5 T 1, T 4 100 3 6 T 1, T 3 100 3 7 T 2, T 6 100 2 8 T 2, T 5 10 3 9 T 3, T 5 10 3 10 T 3, T 4 10 2 11 T 1 100 2 12 T 2 10 1 13 T 3 10 1 14 T 4 5 1 15 T 5 10 2 T 6 100 1 16 Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 46

Integer Linear Program (ILP) l For each clique (test session) i, define: l Integer variable, xi = 1, test session selected, or xi = 0, test session not selected. l Constants, Li = test length, Pi = power. l Constraints to cover all tests: l T 1 is covered if x 1+x 2+x 3+x 4+x 5+x 6+x 11 ≥ 1 l Similar constraint for each test, Tk l Constraints for power: Pi × xi ≤ Pmax Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 47

ILP Objective and Solution l Objective function: l Minimize Σ Li × xi all cliques l Solution: l x 3 = x 8 = x 10 = 1, all other xi’s are 0 l Test session 3 includes T 1 and T 6 l Test session 8 includes T 2 and T 5 l Test session 10 includes T 3 and T 4 l Test length = L 3 + L 8 + L 10 = 120 l Peak power = max {P 3, P 8, P 10} = 3 (Pmax = 4) Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 48

A System Example: ASIC Z* RAM 2 Time=61 Power=241 ROM 1 Time=102 Power=279 RAM 3 Time=38 Power=213 ROM 2 Time=102 Power=279 Random logic 1, time=134, power=295 Random logic 2, time=160, power=352 RAM 4 Time=23 Power=96 RAM 1 Time=69 Power=282 Reg. file Time = 10 Power=95 * Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices, ” Proc. VLSI Test Symp. , April 1993, pp. 4 -9. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 49

ASIC Z Test Schedule-Heuristic Solution 1200 Reg. file Power limit = 900 Power 900 600 RAM 3 RAM 2 Random logic 1 ROM 1 300 RAM 1 RAM 4 0 Random logic 2 ROM 2 200 300 Test time 331 R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI Systems under Power Constraints, ” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 175 -185, June 1997. Copyright Agrawal, 2007 100 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 50 4

ASIC Z: A Better Solution l Obtainable from ILP: l {RL 1, l RL 2, RAM 2} Test length =160 l {RAM 1, ROM 2} Test length = 102 l {RAM 3, RAM 4, RF} Test length = 38 l Total test length = 300 See, E. Larsson and C. P. Ravikumar, “Power-Aware System-Level Test Planning, ” Chapter 6, Section 6. 4. 1 in Power-Aware Testing and Test Strategies for Low Power Devices, P. Girard, N. Nicolici and X. Wen (Eds. ), Springer, 2010. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 51

References l N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. l E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer 2005. l P. Girard, X. Wen and N. A. Touba, “Low-Power Testing, ” in System on Chip Test Architectures, L. -T. Wang, C. E. Stroud and N. A. Touba, editors, Morgan-Kaufman, 2008. l N. Nicolici and P. Girard, Guest Editors, “Special Issue on Low Power Test, ” J. Electronic Testing: Theory and Applications, vol. 24, no. 4, pp. 325– 420, Aug. 2008. l P. Girard, N. Nicolici and X. Wen, Power-Aware Testing and Test Strategies for Low Power Devices, Springer, 2010. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 52

Voltage and Frequency Scaling Test time can be further reduced. l References: l l V. Sheshadri, V. D. Agrawal, and P. Agrawal, “Optimal Power-Constrained So. C Test Schedules With Customizable Clock Rates, ” Proc. 25 th IEEE International System-on-Chip Conf. , Sept. 2012, pp. 271– 276. l V. Sheshadri, V. D. Agrawal, and P. Agrawal, “Optimum Test Schedule for So. C with Specified Clock Frequencies and Supply Voltages, ” Proc. 26 th International Conf. VLSI Design, Jan. 2013, pp. 267– 272. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 53

Variable Test Clock Frequency Selectable clock frequency for each test session. l Increase test clock frequency by factor F l l l Test time divided by F l Test power multiplied by F Proper choice of F for each session can optimize overall test time. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 54

Frequency Factor Fj = Frequency factor of jth session. l Frequency factor limited by: l l Pmax (Power Constraint) l Max. speed of slowest core in session Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 55

ASIC Z Results Nominal clock Prev. Best Optimal Solution Slower clock Copyright Agrawal, 2007 Faster clock ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 56

Constraints on Frequency l Each core’s max. clock rate decided by: l Max. power limit of core (power constraint) l Critical path delay (structural constraint) l Both constraints also influenced by VDD. l Power Constraint: l Structural constraint: (known as Alpha power law) Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 57

Influence of VDD on Test time l Power constrained test: l Structure constrained test: l An optimal VDD can balance the two constraints. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 58

l Optimal VDD Selection Experiments on ISCAS circuits show up to 62% improvement in test time. Simulation and experimental test time plots for s 298* * P. Venkataramani and V. D. Agrawal, “Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. ” Proc. 26 th Int. Conf. VLSI Design, Jan. 2013, pp. 273– 278. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 59

ASIC Z Result Nominal clock Saturates at 268. 3 time units. Prev. Best Optimal Solution Slower clock Faster clock Point A • Cannot further reduce time by increasing Frequency factor. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 60

Assumptions l At Point A: l All test session frequencies are power constrained. l Structural constraint limit >> power constraint limit. l Nominal VDD = 1 V, VTH = 0. 5 V, α = 1 l All cores can be tested at same voltage. l Optimal Copyright Agrawal, 2007 VDD same for all cores. ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 61

Assumptions l At Point A: l All test session frequencies are power constrained. l Structural constraint limit >> power constraint limit. l Nominal VDD = 1 V, VTH = 0. 5 V, α = 1 l All cores can be tested at same voltage. l Optimal Copyright Agrawal, 2007 VDD same for all cores. ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 62

Optimal VDD for ASIC Z Structure constrained test Power constrained test Optimum VDD • 42% reduction in overall test time at optimal VDD. Copyright Agrawal, 2007 ELEC 6270 Spring 13, Lecture 6 Feb 25. . . 63