ELEC 5270 0016270 001Fall 2006 LowPower Design of

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ELEC 5270 -001/6270 -001(Fall 2006) Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D.

ELEC 5270 -001/6270 -001(Fall 2006) Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http: //www. eng. auburn. edu/[email protected] auburn. edu Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 1

Examples of Power Saving and Energy Recovery n Power saving by power transmission at

Examples of Power Saving and Energy Recovery n Power saving by power transmission at high voltage: n n 1000 W transmitted at 100 V, current I = 10 A If resistance of transmission circuit is 1Ω, then power loss = I 2 R = 100 W Transmit at 1000 V, current I = 1 A, transmission loss = 1 W Energy recovery from automobile brakes: n n n Normal brake converts mechanical energy into heat Instead, the energy can be stored in a flywheel, or Converted to electricity to charge a battery Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 2

Reexamine CMOS Gate V 2/Rp V Most energy dissipated here i = Ve-t/Rp. C/Rp

Reexamine CMOS Gate V 2/Rp V Most energy dissipated here i = Ve-t/Rp. C/Rp v(t) p Power i 2 R VI = V 2 e-2 t/Rp. C/Rp C v(t) 3 Rp. C 0 Energy dissipation = Area/2 = CV 2/2 Fall 2006: Dec. 5 V ELEC 5270 -001/6270 -001 Lecture 13 Time, t 3

Charging with Constant Current i=K v(t) = Kt/C C Power i 2 Rp C

Charging with Constant Current i=K v(t) = Kt/C C Power i 2 Rp C 2 V 2 R p /T 2 0 Time (T) to charge capacitor to voltage V v(T) = V = KT/C, or T = CV/K Current, i = K = CV/T Fall 2006: Dec. 5 Time, t Kt/C V 0 t=CV/K Output voltage, v(t) V(t) Power = i 2 Rp = C 2 V 2 Rp/T 2 Energy dissipation = Power × T = (Rp. C/T) CV 2 ELEC 5270 -001/6270 -001 Lecture 13 4

Or, Charge in Steps 0→V/2→V i = Ve-t/Rp. C/2 Rp C V 2 e-2

Or, Charge in Steps 0→V/2→V i = Ve-t/Rp. C/2 Rp C V 2 e-2 t/Rp. C/4 Rp V 2/4 Rp 0 Energy = Area = CV 2/8 V v(t) Power v(t) i 2 Rp V/2 3 Rp. C 6 Rp. C Time, t Total energy = CV 2/8 + CV 2/8 = CV 2/4 Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 5

Energy Dissipation of a Step Voltage step = V/N T E = ∫ V

Energy Dissipation of a Step Voltage step = V/N T E = ∫ V 2 e-2 t/Rp. C/(N 2 Rp) dt 0 = [CV 2/(2 N 2)] (1 – e-2 T/Rp. C) ≈ CV 2/(2 N 2) for large T ≥ 3 Rp. C Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 6

Charge in N Steps Supply voltage 0 → V/N → 2 V/N → 3

Charge in N Steps Supply voltage 0 → V/N → 2 V/N → 3 V/N →. . . NV/N Current, i(t) = Ve-t/Rp. C/NRp Power, i 2(t)Rp = V 2 e-2 t/Rp. C/N 2 Rp Energy = N CV 2/2 N 2 = CV 2/2 N → 0 for N → ∞ Delay Fall 2006: Dec. 5 = N × 3 Rp. C → ∞ for N → ∞ ELEC 5270 -001/6270 -001 Lecture 13 7

References n n C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin,

References n n C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot -Clock n. MOS, ” Proc. Chapel Hill Conf. VLSI, 1985, pp. 1 -17. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y. -C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles, ” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398 -407, Dec. 1994. Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 8

A Conventional Dynamic CMOS Inverter V CK P E P E CK v(t) vin

A Conventional Dynamic CMOS Inverter V CK P E P E CK v(t) vin C vin v(t) Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 9

Adiabatic Dynamic CMOS Inverter P E P E V CK 0 v(t) vin Vf

Adiabatic Dynamic CMOS Inverter P E P E V CK 0 v(t) vin Vf + C vin V-Vf v(t) CK 0 A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic, ” IEEE J. Solid-State Circuits, vol. 30, pp. 311 -315, March 1995. Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 10

Cascaded Adiabatic Inverters vin CK 1 CK 2 CK 1’ CK 2’ input CK

Cascaded Adiabatic Inverters vin CK 1 CK 2 CK 1’ CK 2’ input CK 1 precharge evaluate hold CK 2 CK 1’ CK 2’ Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 11

Complex ADL Gate AB + C A C Vf < Vth B CK A.

Complex ADL Gate AB + C A C Vf < Vth B CK A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic, ” IEEE J. Solid-State Circuits, vol. 30, pp. 311 -315, March 1995. Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 12

Quasi-Adiabatic Logic Two sets of diodes: One controls the charging path (D 1) while

Quasi-Adiabatic Logic Two sets of diodes: One controls the charging path (D 1) while the other (D 2) controls the discharging path n Supply lines have EVALUATE phase ( swings up) and HOLD phase ( swings low) n Fall 2006: Dec. 5 D 1 ELEC 5270 -001/6270 -001 Lecture 13 13

Clocks EVAL. HOLD VDD 0 Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture

Clocks EVAL. HOLD VDD 0 Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 14

Quasi-Adiabatic Logic Design Possible Cases: • The circuit output node X is LOW and

Quasi-Adiabatic Logic Design Possible Cases: • The circuit output node X is LOW and the p. MOS tree is turned ON: X follows as it swings to HIGH (EVALUATE phase) • The circuit node X is LOW and the n. MOS tree is ON. X remains LOW and no transition occurs (HOLD phase) • The circuit node X is HIGH and the p. MOS tree is ON. X remains HIGH and no transition occurs (HOLD phase) • The circuit node X is HIGH and the n. MOS tree is ON. X follows down to LOW. Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 15

A Case Study K. Parameswaran, “Low Power Design of a 32 -bit Quasi-Adiabatic ARM

A Case Study K. Parameswaran, “Low Power Design of a 32 -bit Quasi-Adiabatic ARM Based Microprocessor, ” Master’s Thesis, Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004. Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 16

Quasi-Adiabatic 32 -bit ARM Based Microprocessor Design Specifications n n n Operating voltage: 2.

Quasi-Adiabatic 32 -bit ARM Based Microprocessor Design Specifications n n n Operating voltage: 2. 5 V Operating temperature: 25 o. C Operating frequency: 10 MHz to 100 MHz Leakage current: 0. 5 f. Amps Load capacitance: 6 X 10 -18 F (15% activity) Transistor Count: Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 17

Technology Distribution n Microprocessor has a mix of static CMOS and Quasi-adiabatic components Quasi-Adiabatic

Technology Distribution n Microprocessor has a mix of static CMOS and Quasi-adiabatic components Quasi-Adiabatic Static CMOS Control Units • ARM controller unit • Bus control unit ALU • Adder-subtractor unit • Barrel shifter unit • Booth-multiplier unit Fall 2006: Dec. 5 Pipeline Units • ID unit • IF unit • WB unit • MEM unit ELEC 5270 -001/6270 -001 Lecture 13 18

Power Analysis Datapath Component Power Consumption (m. W) Frequency 25 MHz Power Consumption (m.

Power Analysis Datapath Component Power Consumption (m. W) Frequency 25 MHz Power Consumption (m. W) Frequency 100 MHz Quasiadiabatic Static CMOS Power Saved 32 -bit Adder Subtracter 1. 01 1. 55 44% 1. 29 1. 62 20% 32 -bit Barrel Shifter 0. 9 1. 681 46% 1. 368 1. 8 24% 32 -bit Booth Multiplier 3. 4 5. 8 40% 5. 15 6. 2 17% Power Consumption (m. W) Frequency 25 MHz Fall 2006: Dec. 5 Quasiadiabatic Static CMOS Power Saved 60 m. W 85 m. W 40% ELEC 5270 -001/6270 -001 Lecture 13 19

Power Analysis (Cont’d. ) Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13

Power Analysis (Cont’d. ) Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 20

Area Analysis Area (mm 2) Datapath Component Quasiadiabatic Static CMOS Area Increase 32 -bit

Area Analysis Area (mm 2) Datapath Component Quasiadiabatic Static CMOS Area Increase 32 -bit Adder Subtracter 0. 05 0. 03 66% 32 -bit Barrel Shifter 0. 25 0. 11 120% 32 -bit Booth Multiplier 1. 2 0. 5 140% Chip Area (mm 2) Fall 2006: Dec. 5 Quasiadiabatic Static CMOS Area Increase 1. 55 1. 01 44% ELEC 5270 -001/6270 -001 Lecture 13 21

Summary n In principle, two types of adiabatic logic designs have been proposed: n

Summary n In principle, two types of adiabatic logic designs have been proposed: n Fully-adiabatic n n Adiabatic charging Charge recovery: charge from a discharging capacitor is used to charge the capacitance from the next stage. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y. -C. Chou, “Low-Power Digital Systems Based on Adiabatic. Switching Principles, ” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398 -407, Dec. 1994. Quasi-adiabatic n n Adiabatic charging and discharging Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic, ” IEEE J. Solid-State Circuits, vol. 36, pp. 239 -248, Feb. 2001. Fall 2006: Dec. 5 ELEC 5270 -001/6270 -001 Lecture 13 22