ELEC 256 Saif Zahir Counters An updown kbit

ELEC 256 / Saif Zahir Counters An (up/down) k-bit counter produces a sequence of k-bit binary numbers in a response to a COUNT pulse. A k-bit counter can have up to 2 k different states 7 10 P 163 T 15 2 RCO CLK 6 QD 11 D 5 12 CLK C QC 4 13 B QB 3 A 14 QA 9 LOAD 1 0 1 1 CLR 0 CLR 1 0 Example: 74163 4 -bit synchronous counter Logic. Works Timing Simulation 0 0 1 1 1 0 0 1 0 1 1 UBC / 2000 QD QC QB QA

ELEC 256 / Saif Zahir Design of a 3 -Bit Up-Counter Present C B A Next C+ B+ A+ 0 0 1 1 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0 FF inputs TC TB TA 1 0 1 0 0 0 0 1 0 1 0 1 1 1 1 1 000 100 001 101 010 110 011 111 Next-state Logic CB 00 01 11 10 0 1 1 1 1 1 A TA=1 CB 00 01 11 10 0 0 1 1 1 A CB 00 01 11 10 0 0 1 0 1 1 0 A TB=A TC=AB UBC / 2000

ELEC 256 / Saif Zahir Design of a 3 -Bit Up-Counter Flipflop input equations 1 TA = 1 TB = A TC = AB 1 T S Q T A R S Q B R T S Q C R Count Reset 200 A 0 1 0 1 B 0 0 1 1 CLK UBC / 2000

ELEC 256 / Saif Zahir Design of a 3 -Bit Up-Counter Use D flipflops Present C B A Next C+ B+ A+ 0 0 1 1 1 1 0 0 0 1 1 CB 0 1 0 1 0 1 1 0 00 01 11 10 0 1 1 1 0 0 A da = A FF inputs DC DB DA 1 0 1 0 0 0 0 1 1 0 CB 0 1 1 0 1 0 1 0 00 01 11 10 0 0 1 1 0 0 1 A 000 100 001 101 010 110 011 111 CB 00 01 11 10 0 1 1 1 0 1 A db = Ab + a. B dc = c. B+c. A+Cba UBC / 2000

ELEC 256 / Saif Zahir Up-Counter Using D Flipflops AB D S Q R A D S Q B R D S Q C R Count da = A db = Ab + a. B dc = c. B+c. A+Cba Reset T-FF realization is more efficient - requires less additional combinational logic UBC / 2000

ELEC 256 / Saif Zahir Complex-Counter Design Procedure 1. From specification, draw state-transition diagram to show the desired sequence to be realized by counter. 2. Choose flipflop type, then use FF excitation-table to derive next-state and FF-input equations. • Example: Design the following 5 -state counter PS C B A 0 0 1 1 0 1 0 1 0 0 1 1 NS C+ B+ A+ 0 X 0 1 X 1 0 X 1 1 X 0 0 X 110 FF-inputs TC TB TA 0 X 0 1 X 1 1 X 000 010 0 X 101 011 Using K-maps: Remark: The states that do not appear in the counter squence are treated as don’t care’s! UBC / 2000 tc = Ac + a. C tb = a + B + c ta = Ab. C + Bc

ELEC 256 / Saif Zahir Self-Starting Counters In previous example, a problem may arise of the counter starts in one of the unused states (001, 100, or 111). Since these states were used as don’t-cares, then depending on how these don’t cares were used, counter may exhibit unwanted behavior. 001 111 000 110 100 001 010 101 111 011 100 Bad Design Counter may sequence through unwanted states forever (unless, reset). Better Design: If starts in an unwanted state, counter will go (atmost after one clock-cycle) into its normal state sequence. UBC / 2000

ELEC 256 / Saif Zahir Self-Starting Counters PS C B A 0 0 1 1 0 1 0 1 0 0 1 1 NS C+ B+ A+ 0 1 0 1 1 1 1 0 0 FF-inputs TC TB TA 0 1 1 0 0 1 0 1 1 1 Another possible state diagram for a self-starting counter 0 0 1 1 0 0 000 110 001 010 101 111 011 100 Next-state Logic CB 00 01 11 10 0 1 1 1 0 0 A tc = Ac + a. C CB 00 01 11 10 0 1 1 1 1 A CB 00 01 11 10 0 0 1 1 0 0 0 1 A tb = a + B + c ta = Ab. C + Bc UBC / 2000

ELEC 256 / Saif Zahir Counter Design with RS Flipflops • Example: Design the 5 -state self-starting counter using RS flipflops PS NS FF-inputs C B A C+ B+ A+ RC SC 0 0 1 1 0 1 0 1 0 X 0 1 X 1 0 X X 0 X 0 1 X CB 1 X 1 0 X 00 01 11 10 0 X X 1 X 0 00 01 11 10 0 0 X 1 X X A CB A 0 X 1 1 X 0 0 X CB RB SB 0 X 0 1 X X 0 X 0 1 X 00 01 11 10 0 1 X 1 X 0 00 01 11 10 0 1 X 0 X 1 A CB A RA SA 1 X X 0 X 1 0 X X X 0 0 X 1 X X CB RS-FF excitation table 0 X 1 X X 0 0 X 00 01 11 10 0 X X 1 X 0 X 1 00 01 11 10 0 0 1 0 X 1 X X X 0 A CB A UBC / 2000 Q Q+ R S 0 0 1 1 0 1 X 0 1 0 X tc = A tb = ab+ac ta = c sc = a sb = B sa = b. C

ELEC 256 / Saif Zahir Counter Design with JK Flipflops • Example: Design the 5 -state self-starting counter using JK flipflops PS NS FF-inputs C B A C+ B+ A+ JC KC 0 0 1 1 0 1 0 1 0 X 0 1 X X 00 01 11 10 0 X X 1 X X X 0 CB A 1 X 1 0 X 0 X 1 1 X 0 0 X CB JB KB X X X 0 1 X X X X 1 X X 00 01 11 10 0 1 X X X 1 00 01 11 10 0 X 0 1 X 1 X X A CB A JA KA X X 0 1 X X 1 X 0 X 1 X X X 0 X CB JK-FF excitation table X X X 0 X 1 X X 00 01 11 10 0 0 1 0 X 1 X X 00 01 11 10 0 X X 1 X 0 X 1 A CB A UBC / 2000 Q Q+ J K 0 0 1 1 0 1 0 1 X X 1 0 jc = a jb = 1 ja = b. C kc = A kb = a + c ka = C

ELEC 256 / Saif Zahir Counter Design and Timing JK-FF Realization 1 0 C S J Q C KR Q 1 S J Q C KR Q B S J Q C KR Q CLK A RESET 1 0 Timing Diagram UBC / 2000

ELEC 256 / Saif Zahir Storage Registers S=1 K-bit storage register can be realized by the parallel connection of K D-type flipflops RS or JK flipflops can be used instead as long as they implement the D-FF function! D 3 D Q Q 3 R S=1 D 2 D Q Q 2 R S=1 171 CLK CLR D 3 D 2 D 1 D 0 D 1 D Q 3 Q R Q 2 S=1 Q 1 D 0 Q 0 CLK TTL 74171 package: Quadruple D-type Flipflop with Clear Q 1 D Q R CLR UBC / 2000 Q 0

ELEC 256 / Saif Zahir Registers with Input Enable 171 In the 74171, register contents may change with every positive clock edge. CLK 377 Q 3 CLR CLK EN D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Q 2 D 3 D 2 D 1 D 0 Q 1 Q 0 In the 74377, registers contents change (after the psoitive edge of CLK) only if EN is asserted (EN=0) Potential use of 377 packages in a computer system • Only one of the two 74377 chips can READ from data bus at a time, Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 Data Bus 2: 1 0 MUX 1 Select System Clock D 0 D EN 7 D 0 74377 D EN 7 74377 UBC / 2000

ELEC 256 / Saif Zahir Registers with Output Enables 374 CLK H G F E D C B A OE QH QG QF QE QD QC QB QA The 74374 8 -bit register has tri-stated outputs, which are enabled by the OE input Potential use of 374 packages in a computer system • Only one of the two 74374 chips can WRITE to data bus at a time. Tri-State Buffers CLK D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 OE Data Bus 2: 1 0 MUX 1 Select System Clock Q A Q OE H 74374 Input Data UBC / 2000 Q A Q OE H 74374 Input Data

ELEC 256 / Saif Zahir Shift Registers 4 -Bit Shift-register FF 1 FF 0 Serial input IN D Q Q 0 D Q FF 2 Q 1 D Q FF 3 Q 2 D CLK Correct Operation, assuming positive edge triggered FF 100 IN Q 0 Q 1 Q 2 Q 3 Clk UBC / 2000 Q Q 3 Serial output

ELEC 256 / Saif Zahir Shift Registers Quad right-shift circular shift register using JK flipflops + RESET J K S Q Q 1 J K R S Q R Q 2 J K S Q Q 3 J K R S Q Q 4 R + RESET Shift When RESET=0, Q 1 = 1, Q 2 = Q 3 = Q 4 =0 RESET = 1 RESET = 0, Clk RESET = 0, Clk. . . . Q 1 1 0 0 0 1 0. . Q 2 0 1 0 0 0 1. . Q 3 0 0 1 0 0 0. . Q 4 0 0 0 1 0 0. . Also called Ring Counter UBC / 2000

ELEC 256 / Saif Zahir Shift-Registers with Parallel Load IN. 0 IN. 1 IN. 2 IN. 3 2: 1 MUX SI 0 1 S D Q 0 1 S Q 0 D Q 0 1 S Q 1 D Q 0 1 S Q 2 D Q shift/L CLK SI = serial input Operation - following positive edges of CLK: if shift/L = 1 --> right-shift function is enabled (Q 0 <-- SI, Qi <-- Qi-1) if shift/L = 0 --> parallel-load function is enabled (Qi <-- IN. i ) UBC / 2000 Q 3

ELEC 256 / Saif Zahir Bidirectional Shift-Register SRI SLI 0 1 S D Q 0 1 S Q 0 D Q 0 1 S Q 1 D Q 0 1 S Q 2 D Q Q 4 r/L Shift SRI: serial right input SLI: serial left input Operation - following positive edges of CLK: if r/L = 1 --> right-shift function is enabled (Q 0 <-- SRI, Qi <-- Qi-1) if r/L = 0 --> left-shift function is enabled (Q 4 <-- SLI, Qi <-- Qi+1) UBC / 2000

ELEC 256 / Saif Zahir Finite State machine (FSM) Design • FSMs are sequential machines that can have only a fixed number of states. • Counters are FSMs in which the outputs and the states are identical • In general the outputs and next states of an FSM are functions of the inputs and present states. • The specification of output functions leads to two types of FSMs: – Mealy machines: outputs are functions of inputs and present states – Moore machines: outputs are functions of present states only Inputs X Combinational logic for outputs and nextstates Outputs Z R Moore Machine Mealy Machine CLK Inputs X Combinational logic for next-states only State register R CLK UBC / 2000 Comb. logic for outputs Outputs Z

ELEC 256 / Saif Zahir Sequential Parity Checker Circuit that counts the 1’s in a bit-serial input stream. Odd-parity circuit: asserts its output when input stream contains an odd number of 1’s Even-parity circuit: asserts its output when input stream contains an even number of 1’s Odd-parity sequential machine State-transition table NS = PS xor IN OUT = PS PS input NS Output 0 0 1 1 0 1 0 1 1 0 0 0 1 1 CLK = 1 2 3 4 5 6 7 8 9 10 IN = 0 1 1 0 OUT = 0 0 1 1 1 0 1 Example of input/ouput streams Reset 0 Even [0] 1 1 Odd [1] 0 + 1 0 IN D Clk Realization using a D-FF (a single T-FF can be used instead) UBC / 2000 S Q CRQ RESET Q

ELEC 256 / Saif Zahir Finite State machine Design Procedure – Understand problem » input-output behavior » define states – Obtain an abstract representation of the FSM » state diagrams, state tables – Perform state minimization – Perform state assignment: In an FSM with N=2 n states, n state variables are needed to encode each state (i. e. each state is encoded by n bits) – Choose flipflop types to implement the FSM: use flipflop excitation tables to derive the flipflop input equations. » JK flipflops tend to reduce gate-count » D flipflops tend to simplify design process – Implement the FSM: use K-maps or Boolean logic to simplify next -state (or flipflop input) equations; simplify output equations UBC / 2000

ELEC 256 / Saif Zahir A Simple Vending Machine Problem Statement: • Vending machine delivers a package of gum after receiving 15 cents in coins • Machine has a single coin slot and accepts nickels (N) and dimes only (D) • Machine does not give back change; inserting 2 dimes returns one package only Vending machine controller design Coin Sensor N Vending Machine FSM D OPEN Package Release Mechanism RESET CLK FSM must remember the total amount that has been received, and release a gum package when 15 cents (or 20) have been received. The machine sensor will reject any unknown coins UBC / 2000

ELEC 256 / Saif Zahir A Simple Vending Machine Reset Constructing a state-diagram Possible states S 0: initial (0 cents) state S 1: received 5 cents S 2: received 10 cents S 3: received 15+ cents S 0 [0 ¢] N S 1 [5 ¢] N State-Encoding: • The 4 states of the machine must be encoded in binary. • Since we have four states, we need two bits to encode each state (each bit is called a state-variable) N, D S 3 [15¢] Possible encodings State Q 1 Q 0 S 0 S 1 S 2 S 3 0 0 1 1 S 0 S 1 S 2 S 3 0 1 1 0 0 1 D S 2 [10¢] 1 1 0 0 UBC / 2000 D

ELEC 256 / Saif Zahir A Simple Vending Machine PS inputs Q 1 Q 0 D N D-FF implementation D 1= Q 1+, D 0= Q 0+ Q 1 Q 0 DN D Q 1 Q 0 Q 1 0 0 1 1 1 X X 1 1 DN N D Q 1 K-Map for D 1 Q 1 Q 0 DN D 0 1 0 0 0 1 0 X X 0 0 1 1 X X 0 1 1 1 Q 1 K-Map for D 0 Q 1 N 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 NS outputs Q 1+ Q 0+ OPEN 0 0 1 X 0 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X d 1 = q 1 + d + nq 0 N d 0 = nq 1 + n. Q 0 + Nq 0 + dq 1 open = q 1+ q 0 Q 1 K-Map for OPEN UBC / 2000 0 X 0 0 0 X 1 1 1 X

ELEC 256 / Saif Zahir Vending Machine FSM Implementation with D flipflops Flipflop (next-state) equations d 1 = q 1 + d + nq 0 (Moore machine) d 0 = nq 1 + n. Q 0 + Nq 0 + dq 1 open = q 1+ q 0 Q 1 D D 1 Q 0 N D Q Q 1 Q 0 N OPEN Q 0 N D Q 1 N D 0 Q 1 D CLK RESET UBC / 2000 Q Q 0

ELEC 256 / Saif Zahir FSM Design for a Vending Machine JK-FF Implementation PS inputs Q 1 Q 0 D N 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 NS Q 1+ Q 0+ 0 0 1 X 0 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X FF J 1 K 1 J 0 K 0 outputs OPEN 0 0 1 X 0 1 1 X X X X X 0 1 0 X X X 0 1 1 X 0 0 0 X 1 1 1 X j 1 = d + nq 0 j 0 = n. Q 0 + dq 1 X X X X 0 0 0 X X X 0 1 0 X X X 0 0 0 X k 1 = 0 k 0 = n. Q 1 open = q 1+ q 0 UBC / 2000

ELEC 256 / Saif Zahir Vending Machine FSM Implementation FSM implementation with JK flipflops j 1 = d + nq 0 (Moore Machine) open = q 1+ q 0 k 1 = 0 j 0 = n. Q 0 + dq 1 k 0 = n. Q 1 D J Q 0 N 0 Q Q 1 K OPEN Q 0 N J Q 1 D Q K Q 1 N CLK RESET UBC / 2000 Q 0

ELEC 256 / Saif Zahir Moore and Mealy Machines: State Diagrams Reset S 0 [0] ND/0 Reset OPEN N ND S 1 [0] D Reset/0 N/0 S 2 [0] N, D S 1 ND/0 N D S 0 ND/0 Reset/0 D/0 OPEN S 2 D/1 ND D/1 N/1 S 3 [1] ND/0 S 3 Reset • Complete Moore machine state diagram for vending machine • Outputs are associated with states (graph nodes) Reset/1 • Complete Mealy machine state diagram for vending machine • Outputs are associated with inputs along transition arcs UBC / 2000

ELEC 256 / Saif Zahir Moore and Mealy Machines: State Tables Vending Machine Example PS inputs Q 1 Q 0 D N S 0 S 1 S 2 S 3 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 NS outputs + + Q 1 Q 0 OPEN 0 0 1 X 0 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X 0 0 0 X 1 1 1 X PS inputs Q 1 Q 0 D N S 0 S 1 S 2 S 3 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 NS outputs + + Q 1 Q 0 OPEN 0 0 1 X 0 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X 0 0 0 X 0 1 1 X 1 1 1 X Moore machine state table Mealy machine state table Outputs are associated with states (graph nodes) Outputs are change with inputs UBC / 2000

ELEC 256 / Saif Zahir Binary string Recognizers Example: Construct an FSM that receives a bit-serial binary input W and asserts its output Z whenever its input string has at least two 1’s in sequence. Solution: (1, a) - Input-output behavior CLK W Z (1. b) - Define states (Moore model) 1 2 3 4 5 6 7 8 9 A B C D 0 1 1 1 0 0 0 1 1 1 0 0 S 0: received 0 (most recently) S 1: received 1 (most recently) S 2: received two 1’s in sequence Z=0 Z=1 0 (2) - State diagram (Moore model) S 0 (Z=0) W=0 1 S 1 (0) 0 UBC / 2000 1 S 2 (1) 1

ELEC 256 / Saif Zahir Binary string Recognizers Example: Binary string recognizer (3) - State assignment: 3 states means that we need two bits to represent each state State Q 1 Q 0 S 1 S 2 0 0 1 D 1 0 1 1 CLK W D 0 CLK PS Q 1 Q 0 IN W D NS OUT Q 1+ Q 0+ Z FF D 1 D 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 1 x x 1 1 x x 0 1 d 1 = wq 0 d 0 = wq 0 + w. Q 1 z = q 1 UBC / 2000 Q Q 1 R D Q R Q 0 Z

ELEC 256 / Saif Zahir Binary string Recognizers Example: Binary string recognizer (1. b) - Define states (Mealy model) S 0: received 0 (most recently) S 1: received at least one 1 (most recently) 1/1 (2) - State diagram (Mealy model) S 0 (3) - State assignment (S 0 : = 0 , S 1 : = 1) W=0/Z=0 PS IN Q W NS OUT Q+ Z D T J K 0 0 1 1 0 1 0 1 0 1 1 0 0 1 X X 1 0 0 1 1/0 0 1 0/0 Z W Output Z=WQ D-FF: D=W T-FF: T=W xor Q JK-FF: J=W K=W S 1 D CLK RESET UBC / 2000 Q

ELEC 256 / Saif Zahir Analysis of FSMs Problem Given the hardware schematic of a sequential machine, determine its state behavior and output functions. Example: Analyze the following sequential circuit Solution: 1 - Find JK input equations ja = x jb = x z=b X B X ka = x. B kb = x A J 2 - Compute next-state equations J K CLK RESET a+ = ja A + Ka a = x. A + (X+b)a b+ = jb B + Kb b = x. B + (XA+Xa)b AB X 00 01 11 10 0 1 1 1 0 AB K-map for A+ X A K X A X Q 00 01 11 10 0 1 0 1 1 1 0 1 UBC / 2000 K-map for B+ Q Z=B

ELEC 256 / Saif Zahir FSM Analysis AB X S 0 S 1 S 2 S 3 A B X A+ B+ Z (=B) 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 More Machine: output isf function of present state only, Z=B 00 01 11 10 0 1 1 1 0 AB X X=0 00 01 11 10 0 1 0 1 1 1 0 1 X=1 S 0 Z=0 K-map for A+ S 3 Z=1 1 0 S 1 Z=1 UBC / 2000 1 K-map for B+ 1 S 2 Z=0 0 0

ELEC 256 / Saif Zahir Sequential (Bit-Serial) Adder Design Sequential adder operation to add two numbers A=ak ak-1. . . a 1 a 0 and B=bk bk-1. . . b 1 b 0 - start by adding a 0 and a 0 - output sum bit s 0 and store carry bit c 0 so that it is added to bits a 1 and b 1 in the next clock cycle Z Clock cycle - repeat the procedure for 1 1 1 0 4 3 2 1 LSB SUM bits ai and bi 1 0 0 1 A (output si and store carry bit ci) 0 1 0 0 0 1 B Direct Design 0 0 1 0 Implement design using a combinational logic block that generates next-state and output functions, and a storage Present state element (D-FF) to store present state Mealy Model C Next state 1 Q S D QRC CLK CLR UBC / 2000

ELEC 256 / Saif Zahir Sequential Adder Design using Formal Methods AB=11/Z=0 Inputs: A, B Output: Z=SUM RESET States (last carry bit): S 0: carry was 0 S 1: carry was 1 PS Q IN A B NS Q+ 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 1 1 OUT Z S 0 S 1 00/0 01/1 10/1 D FF J K 0 1 1 0 0 0 0 1 x x 1 0 0 1 1 1 x x 1 0 00/1 AB Q 00 01 11 10 0 1 0 1 X X 00 01 11 10 0 X X X 1 1 0 0 AB Q K-map for J X K-map for K 0 Z = A xor B xor Q D= Q 01/0 10/0 11/1 j = ab UBC / 2000 k = AB

ELEC 256 / Saif Zahir Moore Machine Realization of Sequential Adder More states are required for Moore Model S 0: S 1: S 2: S 3: C=0 and Z=0 (C=carry, Z: sum) C=0 and Z=1 C=1 and Z=0 C=1 and Z=1 Two flipflops are needed to implement the Moore Model sequential adder State Diagram 00 S 0 Z=0 RESET Ex. : Implement this state diagram using D, flipflops and JK flipflops 11 01 10 S 2 Z=0 11 01 10 00 01 10 11 00 01 10 S 0 Z=0 00 S 2 Z=0 11 UBC / 2000