EL 547 Introduction to CMOS VLSI Design Lecture

EL 547: Introduction to CMOS VLSI Design Lecture 15: Design for Testability Garrett S. Rose Fall 2006 Slides adapted from Harris’ slides from Harvey Mudd. Copyright 2005 Addison-Wesley.

Outline q Testing – Logic Verification – Silicon Debug – Manufacturing Test q Fault Models q Observability and Controllability q Design for Test – Scan – BIST q Boundary Scan L 15: Design for Testability CMOS VLSI Design 2

Testing q Testing is one of the most expensive parts of chips – Logic verification accounts for > 50% of design effort for many chips – Debug time after fabrication has enormous opportunity cost – Shipping defective parts can sink a company q Example: Intel FDIV bug – Logic error not caught until > 1 M units shipped – Recall cost $450 M (!!!) L 15: Design for Testability CMOS VLSI Design 3

Logic Verification q Does the chip simulate correctly? – Usually done at HDL level – Verification engineers write test bench for HDL • Can’t test all cases • Look for corner cases • Try to break logic design q Ex: 32 -bit adder – Test all combinations of corner cases as inputs: • 0, 1, 2, 231 -1, -231, a few random numbers q Good tests require ingenuity L 15: Design for Testability CMOS VLSI Design 4

Silicon Debug q Test the first chips back from fabrication – If you are lucky, they work the first time – If not… q Logic bugs vs. electrical failures – Most chip failures are logic bugs from inadequate simulation – Some are electrical failures • Crosstalk • Dynamic nodes: leakage, charge sharing • Ratio failures – A few are tool or methodology failures (e. g. DRC) q Fix the bugs and fabricate a corrected chip L 15: Design for Testability CMOS VLSI Design 5

Shmoo Plots q How to diagnose failures? – Hard to access chips • Picoprobes • Electron beam • Laser voltage probing • Built-in self-test q Shmoo plots – Vary voltage, frequency – Look for cause of electrical failures L 15: Design for Testability CMOS VLSI Design 6

Manufacturing Test q A speck of dust on a wafer is sufficient to kill chip q Yield of any chip is < 100% – Must test chips after manufacturing before delivery to customers to only ship good parts q Manufacturing testers are very expensive – Minimize time on tester – Careful selection of test vectors L 15: Design for Testability CMOS VLSI Design 7

Testing Your Chips q If you don’t have a multimillion dollar tester: – Build a breadboard with LED’s and switches – Hook up a logic analyzer and pattern generator – Or use a low-cost functional chip tester L 15: Design for Testability CMOS VLSI Design 8

Testoster. ICs q Ex: Testoster. ICs functional chip tester – Designed by clinic teams and David Diaz at HMC – Reads your IRSIM test vectors, applies them to your chip, and reports assertion failures L 15: Design for Testability CMOS VLSI Design 9

Stuck-At Faults q How does a chip fail? – Usually failures are shorts between two conductors or opens in a conductor – This can cause very complicated behavior q A simpler model: Stuck-At – Assume all failures cause nodes to be “stuck-at” 0 or 1, i. e. shorted to GND or VDD – Not quite true, but works well in practice L 15: Design for Testability CMOS VLSI Design 10

Examples L 15: Design for Testability CMOS VLSI Design 11

Observability & Controllability q Observability: ease of observing a node by watching external output pins of the chip q Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip q Combinational logic is usually easy to observe and control q Finite state machines can be very difficult, requiring many cycles to enter desired state – Especially if state transition diagram is not known to the test engineer L 15: Design for Testability CMOS VLSI Design 12

Test Pattern Generation q Manufacturing test ideally would check every node in the circuit to prove it is not stuck. q Apply the smallest sequence of test vectors necessary to prove each node is not stuck. q Good observability and controllability reduces number of test vectors required for manufacturing test. – Reduces the cost of testing – Motivates design-for-test L 15: Design for Testability CMOS VLSI Design 13

Test Example SA 1 q q q q SA 0 A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y q Minimum set: L 15: Design for Testability CMOS VLSI Design 14

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} SA 0 {1110} q Minimum set: L 15: Design for Testability CMOS VLSI Design 15

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} {1010} SA 0 {1110} q Minimum set: L 15: Design for Testability CMOS VLSI Design 16

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} {1010} {0100} SA 0 {1110} {0110} q Minimum set: L 15: Design for Testability CMOS VLSI Design 17

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} {1010} {0100} {0110} SA 0 {1110} {0110} {0111} q Minimum set: L 15: Design for Testability CMOS VLSI Design 18

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} {1010} {0100} {0110} {1110} SA 0 {1110} {0110} {0111} {0110} q Minimum set: L 15: Design for Testability CMOS VLSI Design 19

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} {1010} {0100} {0110} {1110} {0110} SA 0 {1110} {0110} {0111} {0110} {0100} q Minimum set: L 15: Design for Testability CMOS VLSI Design 20

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} {1010} {0100} {0110} {1110} {0101} SA 0 {1110} {0110} {0111} {0110} {0100} {0110} q Minimum set: L 15: Design for Testability CMOS VLSI Design 21

Test Example q q q q A 3 A 2 A 1 A 0 n 1 n 2 n 3 Y SA 1 {0110} {1010} {0100} {0110} {1110} {0101} {0110} SA 0 {1110} {0110} {0111} {0110} {0100} {0110} {1110} q Minimum set: {0100, 0101, 0110, 0111, 1010, 1110} L 15: Design for Testability CMOS VLSI Design 22

Design for Test q Design the chip to increase observability and controllability q If each register could be observed and controlled, test problem reduces to testing combinational logic between registers. q Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically. L 15: Design for Testability CMOS VLSI Design 23

Scan q Convert each flip-flop to a scan register – Only costs one extra multiplexer q Normal mode: flip-flops behave as usual q Scan mode: flip-flops behave as shift register q Contents of flops can be scanned out and new values scanned in L 15: Design for Testability CMOS VLSI Design 24

Scannable Flip-flops L 15: Design for Testability CMOS VLSI Design 25

Built-in Self-test q Built-in self-test lets blocks test themselves – Generate pseudo-random inputs to comb. logic – Combine outputs into a syndrome – With high probability, block is fault-free if it produces the expected syndrome L 15: Design for Testability CMOS VLSI Design 26

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator Step Q 0 111 1 2 3 4 5 6 L 15: Design for Testability 7 CMOS VLSI Design 27

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator Step Q 0 111 1 110 2 3 4 5 6 L 15: Design for Testability 7 CMOS VLSI Design 28

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator Step Q 0 111 1 110 2 101 3 4 5 6 L 15: Design for Testability 7 CMOS VLSI Design 29

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator Step Q 0 111 1 110 2 101 3 010 4 5 6 L 15: Design for Testability 7 CMOS VLSI Design 30

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator Step Q 0 111 1 110 2 101 3 010 4 100 5 6 L 15: Design for Testability 7 CMOS VLSI Design 31

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator Step Q 0 111 1 110 2 101 3 010 4 100 5 001 6 L 15: Design for Testability 7 CMOS VLSI Design 32

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator L 15: Design for Testability Step Q 0 111 1 110 2 101 3 010 4 100 5 001 6 011 7 CMOS VLSI Design 33

PRSG q Linear Feedback Shift Register – Shift register with input taken from XOR of state – Pseudo-Random Sequence Generator L 15: Design for Testability Step Q 0 111 1 110 2 101 3 010 4 100 5 001 6 011 7 CMOS VLSI Design 111 (repeats) 34

BILBO q Built-in Logic Block Observer – Combine scan with PRSG & signature analysis L 15: Design for Testability CMOS VLSI Design 35

Boundary Scan q Testing boards is also difficult – Need to verify solder joints are good • Drive a pin to 0, then to 1 • Check that all connected pins get the values q Through-hold boards used “bed of nails” q SMT and BGA boards cannot easily contact pins q Build capability of observing and controlling pins into each chip to make board test easier L 15: Design for Testability CMOS VLSI Design 36

Boundary Scan Example L 15: Design for Testability CMOS VLSI Design 37

Boundary Scan Interface q Boundary scan is accessed through five pins – TCK: test clock – TMS: test mode select – TDI: test data in – TDO: test data out – TRST*: test reset (optional) q Chips with internal scan chains can access the chains through boundary scan for unified test strategy. L 15: Design for Testability CMOS VLSI Design 38

Summary q Think about testing from the beginning – Simulate as you go – Plan for test after fabrication q “If you don’t test it, it won’t work! (Guaranteed)” L 15: Design for Testability CMOS VLSI Design 39

Faults q Hypothesize possible faults for which to test (may be layout dependent): – Stuck-at-0 (SA 0), stuck-at-1 (SA 1) • Node tied to Vdd or GND – Bridging (shorting) • Two wires tied together on one or more layers – Stuck-open • Break in a wire disconnects two wires – Delay faults • Parameter variations slow down a gate – Path-delay faults • Cumulative delay faults along a path – Multi-fault [©Hauck] • Test for combination of faults not one at a time Spring 2006 CMOS VLSI Design EE 5324 - VLSI 40

Fault Models q Stuck-at covers most of the faults – Shown: short (a, g), open (b) Z a x 1 g a, g : b: x 3 x 1 sa 1 x 1 sa 0 or x 2 sa 0 b x 2 [©Prentice Hall] Spring 2006 CMOS VLSI Design EE 5324 - VLSI 41

Fault Models (cont. ) q Stuck-at does not cover all faults – Example: Sequential effect: x 2 x 1 Z x 1 x 2 Z 0 1 1 x 1 0 Zn-1 x 2 – Needs two vectors to detect q Other options: – Use stuck-open or stuck-short models – Problem: too expensive! [©Prentice Hall] Spring 2006 CMOS VLSI Design EE 5324 - VLSI 42

Test Vector Generation: First Shot F in presence of different stuck-at faults ABC F Fm 0 Fn 0 Fp 0 Fq 0 Fm 1 Fn 1 Fp 1 Fq 1 000 001 010 011 100 101 110 111 1 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 fault table ABC m 0, n 0, p 0 q 0 001 010 011 100 101 110 111 m 1 n 1 1 p 1, q 1 1 1 A B C' m p n q F = AB + C' 1 1 Spring 2006 1 0 1 1 [©Hauck] CMOS VLSI Design EE 5324 - VLSI 43

Test Vector Generation: Path Sensitization q Work forward and backward from node of interest to determine values of inputs to test for fault q At the site of the fault, assign a logical value complementary to the fault q Select a path from the circuit inputs through the site of the fault to an output, the path is sensitized if the inputs to the gates along the path are set so as to propagate the value at the fault site [©Hauck] q. Spring Determine the primary inputs that will produce the 2006 CMOS VLSI Design EE 5324 - VLSI 44

Path Sensitization Example q Trigger the fault q Make it propagate to output 1 Fault enabling 1 1 Fault propagation 1 sa 0 1 Out 1 0 0 [©Prentice Hall] Spring 2006 CMOS VLSI Design EE 5324 - VLSI 45