EKT 124 3 DIGITAL ELEKTRONIC 1 CHAPTER 3

EKT 124 / 3 DIGITAL ELEKTRONIC 1 CHAPTER 3 Sequential Logic/ Circuits: Shift Register

Shift Register Basic shift register function Serial in/Serial out shift registers (SISO) Serial in/Parallel out shift registers (SIPO) Parallel in/Serial out shift registers (PISO) Parallel in/Parallel out shift registers (PIPO) q Bidirectional shift registers q Shift register applications q q q

Sequential Logic Circuits Combinational outputs Combinational logic Memory outputs Memory elements Inputs Sequential circuit = Combinational logic + Memory Elements Current State of A sequential Circuit: Value stored in memory elements (value of state variables). State transition: A change in the stored values in memory elements thus changing the sequential circuit from one state to another state.

Registers q A register is a memory device that can be used to store more than one-bit information q A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the registers q ……….

Registers q An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits. Example: 74 LS 175 4 -bit register 74 LS 175 1 D Q D CLR 2 D Q D CLR 3 D CLK /CLR Q Q D CLR 4 D Q Q Q D CLR Q 1 Q /1 Q CLK CLR 2 Q /2 Q 1 D 3 Q 2 D /3 Q 4 Q /4 Q 3 D 4 D 1 Q 1 Q 2 Q 2 Q 3 Q 3 Q 4 Q 4 Q 74 LS 175

Shift Registers q Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle) – Shift Left is towards MSB Q 3 Q 2 Q 1 0 1 Q 3 Q 2 Q 1 Q 0 1 1 LSI 1 1 1 Q 0 LSI – Shift Right (or Shift Up) is towards MSB Q 3 Q 2 Q 1 RSI 0 1 1 Q 0 1 Q 3 Q 2 Q 1 RSI 0 1 Q 0 1

Basic Shift Register Functions q consist of an arrangement of flip-flops q important in applications involving storage and transfer of data (data movement) in digital system q used for storing and shifting data (1 s and 0 s) entered into it from an external source and possesses no characteristic internal sequence of states. q Generally, D flip-flops are usually used to store and move data

The flip-flop as a storage element When a 1 is on D, Q becomes a 1 at triggering edge of CLK or remains a 1 if already in the SET state When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state

Basic data movement in shift registers (Four bits are used for illustration. The bits move in the direction of the arrows. )

Types of Shift Registers q Serial In / Serial Out Shift Registers (SISO) q Serial In /Parallel Out Shift Registers (SIPO) q Parallel In / Serial Out Shift Registers (PISO) q Parallel In / Parallel Out Shift Registers (PIPO)

Serial In, Serial Out Shift Registers (SISO) Serial In Clock D Q SRG n > SI CLK D Q For a n-bit SRG: Serial Out = Serial In delayed by n clock period CLK · · · D Q CLK SO Serial Out 4 -bit shift register example: Serial in: 1 0 1 1 0 0 1 1 1 0 Serial out: - - 1 0 1 1 0 0 Clock:

Serial In, Serial Out Shift Registers (SISO)

Serial In, Serial Out Shift Registers (SISO)

Serial In, Parallel Out Shift registers (SIPO) Serial In D Q Clock CLK D Q 1 Q 2 Q > SI SRG n 1 Q 2 Q · SO · n. Q · Serial to Parallel Converter CLK · · · D Q CLK n. Q Example: 4 -bit shift register serin: 1 0 1 1 0 0 1 1 1 0 1 Q: - 101100111 2 Q: - - 10110011 3 Q: - - - 1011001 4 Q: - - 101100 clock:

Serial In, Parallel Out Shift registers (SIPO) q Data bits entered serially (right-most bit first) q Difference from SISO is the way data bits are taken out of the register – in parallel. q Output of each stage is available

Example: The states of 4 -bit register (SRG 4) for the data input and clocks waveforms. Assume the register initially contains all 1 s

Parallel In, Serial Out Shift Registers (PISO) CLOCK LOAD/SHIFT Serial in S 1 D L D Q CLK S 2 D 1 Q D Q L 2 Q CLK Parallel to Serial Converter Load/Shift=1 Di Q i Load/Shift=0 Qi Qi+1 ND · · · S L · · · D Q CLK NQ Serial out

4 -bit parallel in/serial out shift register (PISO)

Parallel In, Parallel Out Shift Register (PIPO) CLOCK LOAD/SHIFT Serial In S 1 D L D Q CLK S 2 D L 2 Q CLK · · · S ND D Q L General Purpose: Makes any kind of (left) shift register 1 Q · · · D Q CLK NQ

Parallel In, Parallel Out Shift Register (PIPO) q Immediately following simultaneous entry of all data bits, it appears on parallel output.

Types of Shift Registers Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register being: 1) SIPO - the register is loaded with serial data, one bit at a time, with the stored data being available in parallel form. 2) SISO - the data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a left or right direction under clock control. 3) PISO - the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control. 4) PIPO - the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.

Bi-directional Shift Registers q Data can be shifted left q Data can be shifted right q A parallel load maybe possible q 74 HC 194 is an bidirectional universal shift register

Bi-directional Universal Shift Registers 11 1 Modes: Hold Load Shift Right Shift Left 10 9 7 6 5 4 3 2 CLK CLR S 1 S 0 LIN D C B A RIN 74 x 194 QD QC QB QA 12 R L 13 14 15 4 -bit Bi-directional Universal (4 -bit) PIPO Function Hold Shift right/up Shift left/down Load Mode S 1 S 0 0 1 1 Next state QA* QB* QC* QA QB QC RIN QA QB QB QC QD A B C QD* QD QC LIN D

4 -bit Johnson counters n Serial output connected back to serial input n The complement of the output (Q’) is fedback into 1 st FF.

4 -bit Johnson Ring Counter Clock FFA FFB FFC FFD Pulse No 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1 q This inversion of Q before it is fed back to input D causes the counter to "count" in a different way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4 -bit counter, "0001"(1), "0010"(2), "0100"(4), "1000"(8) and repeat, the Johnson counter counts up and then down as the initial logic "1" passes through it to the right replacing the preceding logic "0". q A 4 -bit Johnson ring counter passes blocks of four logic "0" and then four logic "1" thereby producing an 8 -bit pattern. q As the inverted output Q is connected to the input D this 8 -bit pattern continually repeats. For example, "1000", "1110", "1111", "0011", "0000”

Five-bit Johnson counters

10 -bit ring counter Assume initial state: (Q 0 ---Q 9) =1010000000

4 -bit Ring Counter q Synchronous Ring Counter is preset so that exactly one data bit in the register is set to logic "1" with all the other bits reset to "0". q To achieve this, a "CLEAR" signal is firstly applied to all the flip-flops together in order to "RESET" their outputs to a logic "0" level and then a "PRESET" pulse is applied to the input of the first flip-flop (FFA) before the clock pulses are applied. q This then places a single logic "1" value into the circuit of the ring counter. q On each successive clock pulse, the counter circulates the same data bit between the four flip-flops over and over again around the "ring" every fourth clock cycle. q In order to cycle the data correctly around the counter we must first "load" the counter with a suitable data pattern as all logic "0"'s or all logic "1"'s outputted at each clock cycle would make the ring counter invalid.

ROTATION OF RING COUNTER Since the ring counter has four distinct states, it is also known as a "modulo-4" or "mod 4" counter with each flip-flop output having a frequency value equal to one-fourth or a quarter (1/4) that of the main clock frequency.

Shift Register Applications q State Registers § Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position (i. e. a finite memory machine) § Very effective for sequence detectors q Serial Interconnection of Systems § keep interconnection cost low with serial interconnect q Bit Serial Operations § Bit serial operations can be performed quickly through device iteration § Iteration (a purely combinational approach) is expensive (in terms of # transistors, chip area, power, etc). § A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation

Shift Register Applications Example: Serial Interconnection of Systems CLOCK Transmitter Control Circuits Parallel Data from A-to-D converter n Parallelto-serial converter Control /SYNC Receiver Circuits Serial DATA One bit Parallel Data to D -to-A converter Serial-toparallel converter n

Shift Register Applications Example: 8 -Bit Serial Adder CTL CLK > > x 7 x 6 x 5 7 6 5 y 7 y 6 y 5 7 6 5 x 0 . . . Sequential Implementation of: Z[7. . 0] = X[7. . 0] + Y[7. . 0] 0 y 0. . . 0 D Q Cin A FA Cout CLK CLR B S > CLEAR_C V 7 6 5 z 7 z 6 z 5 . . . 0 z 0

Shift Register Applications Example: The shift register as a time-delay device

Shift Register Applications Example: Simplified logic diagram of a serial-to-parallel converter