EEL 5708 High Performance Computer Architecture Lecture 3

EEL 5708 High Performance Computer Architecture Lecture 3 Review: Instruction Sets Sept 1, 2006 Lotzi Bölöni Fall 2006 EEL 5708/Bölöni Lec 3. 1

Acknowledgements • All the lecture slides were adopted from the slides of David Patterson (1998, 2001) and David E. Culler (2001), Copyright 1998 -2002, University of California Berkeley Fall 2006 EEL 5708/Bölöni Lec 3. 2

Instruction sets Fall 2006 EEL 5708/Bölöni Lec 3. 3

The Instruction Set: a Critical Interface software instruction set hardware Fall 2006 EEL 5708/Bölöni Lec 3. 4

Levels of Representation temp = v[k]; High Level Language Program Compiler Assembly Language Program Assembler Machine Language Program v[k] = v[k+1]; v[k+1] = temp; lw lw sw sw 0000 1010 1100 0101 1001 1111 0110 1000 $15, $16, $15, 1100 0101 1010 0000 0110 1000 1111 1001 0($2) 4($2) 1010 0000 0101 1100 1111 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Machine Interpretation Control Signal Specification ALUOP[0: 3] <= Inst. Reg[9: 11] & MASK ° ° Fall 2006 EEL 5708/Bölöni Lec 3. 5

Instruction Set Architecture. . . the attributes of a [computing] system as seen by the programmer, i. e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964 SOFTWARE -- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions Fall 2006 EEL 5708/Bölöni Lec 3. 6

Basic ISA Classes Accumulator: 1 address add A acc ¬ acc + mem[A] 1+x address addx A acc ¬ acc + mem[A + x] Stack: 0 address add tos ¬ tos + next General Purpose Register: 2 address add A B EA(A) ¬ EA(A) + EA(B) 3 address add A B C EA(A) ¬ EA(B) + EA(C) Load/Store: 3 address add Ra Rb Rc Ra ¬ Rb + Rc load Ra Rb Ra ¬ mem[Rb] store Ra Rb mem[Rb] ¬ Ra Fall 2006 EEL 5708/Bölöni Lec 3. 7

Instruction Formats Variable: … Fixed: Hybrid: • Addressing modes –each operand requires address specifier => variable format • code size => variable length instructions • performance => fixed length instructions –simple decoding, predictable operations • With load/store instruction arch, only one memory address and few addressing modes • => simple format, address mode given by opcode Fall 2006 EEL 5708/Bölöni Lec 3. 8

Execution Cycle Instruction Obtain instruction from program storage Fetch Instruction Determine required actions and instruction size Decode Operand Locate and obtain operand data Fetch Execute Result Compute result value or status Deposit results in storage for later use Store Next Instruction Fall 2006 Determine successor instruction EEL 5708/Bölöni Lec 3. 9

MIPS instruction set Fall 2006 EEL 5708/Bölöni Lec 3. 10

Review: MIPS R 3000 (core) r 0 r 1 ° ° ° r 31 PC lo hi 0 Programmable storage Data types ? 2^32 x bytes Format ? 31 x 32 -bit GPRs (R 0=0) Addressing Modes? 32 x 32 -bit FP regs (paired DP) HI, LO, PC Arithmetic logical Add, Add. U, Sub. U, And, Or, Xor, Nor, SLTU, Add. IU, SLTIU, And. I, Or. I, Xor. I, LUI SLL, SRA, SLLV, SRAV Memory Access LB, LBU, LHU, LWL, LWR SB, SH, SWL, SWR Control 32 -bit instructions on word boundary J, JAL, JR, JALR Fall 2006 BEq, BNE, BLEZ, BGTZ, BLTZ, BGEZ, BLTZAL, BGEZAL EEL 5708/Bölöni Lec 3. 11

MIPS Addressing Modes & Formats • Simple addressing modes • All instructions 32 bits wide Register (direct) op rs rt rd register Immediate Base+index op rs rt immed register PC-relative op rs PC rt Memory + immed Memory + • Register Indirect? Fall 2006 EEL 5708/Bölöni Lec 3. 12