EEL 47205721 Reconfigurable Computing Greg Stitt Associate Professor

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EEL 4720/5721 Reconfigurable Computing Greg Stitt Associate Professor

EEL 4720/5721 Reconfigurable Computing Greg Stitt Associate Professor

Instructors n Dr. Greg Stitt n n n gstitt@ece. ufl. edu http: //www. gstitt.

Instructors n Dr. Greg Stitt n n n [email protected] ufl. edu http: //www. gstitt. ece. ufl. edu Office Hours: M Period 2, W Period 4 n n n (Benton 323) Also, by appointment TAs n n Nayanatara Kolhapuri Suresh ([email protected] edu) Seyed Mehrdad Hashemi ([email protected] edu)

Course Website n 2 sites n n http: //www. gstitt. ece. ufl. edu/courses/eel 4720_5721/

Course Website n 2 sites n n http: //www. gstitt. ece. ufl. edu/courses/eel 4720_5721/ n Linked off my website n Includes all slides, labs, reading assignments, announcements, etc. Canvas n http: //lss. at. ufl. edu/� n n Select Canvas Login with Gator. Link account Used for posting grades, turning in projects, student discussions Email Policy n When sending an email, include the class name in brackets n e. g. [EEL 5721] Question about project 2

Grading n Grading: n n n Tests will be 50 minutes, during normal class

Grading n Grading: n n n Tests will be 50 minutes, during normal class time EDGE students have 3 day window for tests n n n Mid-term 1: 25% (Wed. October 14 th) Mid-term 2: 25% (Wed. December 9 th) Labs: 25% Project: 25% October 13 th-15 th and December 7 th-9 th Final grade: curved average of all components 5721 may possibly have different tests,

Lab Assignments n Linked off main website n n n http: //www. gstitt. ece.

Lab Assignments n Linked off main website n n n http: //www. gstitt. ece. ufl. edu/courses/eel 4720_5721/labs/ Intended to familiarize with FPGA boards, VHDL Initial labs will be individual n Groups allowed when using boards n n There are ~100 students in this class and ~10 boards Will announce group policies when discussing corresponding labs n Likely 2 people per group

Research Project n 2 options n n n Assigned project Proposed project Assigned project

Research Project n 2 options n n n Assigned project Proposed project Assigned project n n Most of the class will do this project There will be several alternatives for different group sizes n n n EDGE students will have a project appropriate for a individual participant EDGE students can participate in groups if desired Important: I will require a minimum number of groups to deal with the small number of boards

Research Project, Cont. n Proposed project n n Topic subject to instructor approval Due

Research Project, Cont. n Proposed project n n Topic subject to instructor approval Due to the limited number of boards, the proposed project option must be earned n n Suggestion: find algorithm in your area of interest, use reconfigurable computing to improve performance n n Will allow those with best grades or project ideas to do their own project Image processing, bioinformatics, physics, chemistry, AI, etc. If interested in research, email me later in the semester n Will try to find a project that helps towards Ph. D

Reading Material n No required textbook n n Research papers n n n Optional

Reading Material n No required textbook n n Research papers n n n Optional books on website and in syllabus Check class website for material associated with each lecture Will also post slides when used Important: VHDL resources posted on website

Prerequisites n You should be familiar with basics of: n Digital design n n

Prerequisites n You should be familiar with basics of: n Digital design n n Architecture n n Registers, muxes, adders, finite-state machines, etc. Controller+Datapath Memories Pipelining Assumes no knowledge of reconfigurable computing or VHDL

Goals n Understanding of issues related to RC (reconfigurable computing) n n n Detailed

Goals n Understanding of issues related to RC (reconfigurable computing) n n n Detailed investigation of a specific application n n Architectures Tools Design methodologies Performance analysis Etc. Research project Publish! n Outstanding projects will be submitted to conferences

Academic Dishonesty n Unless told otherwise, labs and homework assignments must be done individually

Academic Dishonesty n Unless told otherwise, labs and homework assignments must be done individually n n Groups must obtain permission to use larger size n n May be allowed for difficult projects Collaboration is allowed (and encouraged), but within limits n n All assignments will be checked for cheating Can discuss problems, how to use tools etc. Cannot show code, solutions, etc. I will be using automatic cheat checking Cheating penalties n n First instance - 0 on corresponding assignment Second - 0 for entire class

Attendance Policy n n Attendance is optional, but highly recommended If you are not

Attendance Policy n n Attendance is optional, but highly recommended If you are not an EDGE student, please don’t disappear! n n n I answer a lot of questions before and after lecture I will not be pleased if you come to my office or send me an email with the same questions If you are sick, stay at home! n n If obviously sick, you will be asked to leave Missed tests can be retaken with doctor’s note

What is Reconfigurable Computing? n Reconfigurable computing (RC) is the study of architectures that

What is Reconfigurable Computing? n Reconfigurable computing (RC) is the study of architectures that can adapt (after fabrication) to a specific application or application domain n Involves architecture, tools, CAD, design automation, algorithms, languages, etc.

What is Reconfigurable Computing? Alternatively, RC is a way of implementing circuits without fabricating

What is Reconfigurable Computing? Alternatively, RC is a way of implementing circuits without fabricating a device n n n Essentially allows circuits to be implemented as “software” Circuits are no longer synonymous with hardware n n RC devices are programmable by downloading bits, just like microprocessors Difference is that microprocessor bits specify instructions, whereas RC bits specify circuit structures a Microprocessor Binaries 001010010 FPGA Binaries (Bitfile) 001010010 Processor x Bits loaded into logic blocks, switch matrices, memories, etc. Bits loaded into program memory 0010 … b 0010 … FPGA Processor c y

Why is RC important? n Performance n n Often orders of magnitude faster than

Why is RC important? n Performance n n Often orders of magnitude faster than microprocessors Low power consumption n A few RC devices can provide similar performance as large cluster at a fraction of the power n n Also smaller, cheaper, etc. Motivating example: Novo-G n n n FPGA-based supercomputer 192 large Altera Stratix III FPGAs 24 Linux nodes Speedups of 100, 000 x to 550, 000 x for computation biology apps (compared to 2. 4 GHz Opteron) Performance similar to top supercomputers However, power consumption is only 8 kilowatts compared to 2 -7 megawatts

Reminders n URGENT n n n Lab 0 – Vivado and VHDL Tutorial Start

Reminders n URGENT n n n Lab 0 – Vivado and VHDL Tutorial Start reading VHDL tutorial on class website Read RC survey linked off website