EEL 4712 Digital Design MIPS Processor Stored Program

EEL 4712 Digital Design (MIPS Processor)

Stored Program l Instructions and data stored in memory. l Only difference between two applications (for example, a text editor and a video game), is the sequence of instructions. l To run a new program: No rewiring required u Simply store new program in memory u The processor hardware executes the program: u q fetches (reads) the instructions from memory in sequence q performs the specified operation l The program counter (PC) keeps track of the current instruction. 2

High-level Programs to Instructions l Therefore with the help of a compiler (and assembler), to run applications all we need is a means to interpret (or “execute”) machine instructions. l Usually the application calls on the operating system and libraries to provide special functions. 3

Architecture Layers l Architecture: the programmer’s view of the computer u Defined by instructions (operations) and operand locations l Microarchitecture: how to implement an architecture in hardware l The microarchitecture is built out of “logic” circuits and memory elements (what we learnt so far : D). l All logic circuits and memory elements are implemented in the physical world with transistors. 4

Interpreting Instructions to Machine Codes l Start with opcode l Opcode tells how to parse the remaining bits l If opcode is all 0’s R-type instruction u Function bits tell what instruction it is u l Otherwise u Opcode tells what instruction it is ☼A processor is a machine code interpreter build in hardware! 5

Processor l A processor execute a set of instructions of a computer program by performing the basic arithmetic, logic, controlling, input/output operations specified by the instructions. https: //en. wikipedia. org/wiki/Central_processing_unit 6

MIPS Processor l MIPS: Microprocessor without Interlocked Pipelined Stages M e m ory C PU C op ro ce ssor 1 (F P U ) R e giste rs $0 $0 $31 Arithm e tic Logic unit Prog. Counter Control M ultip ly divide Lo Arithm e tic unit Hi C op ro ce ssor 0 (tra ps a nd m e m ory) R e giste rs Ba d V Ad dr C a use S ta tu s EPC 7

MIPS Instructions l Here is a subset of MIPS instructions: u R-type instructions: and, or, add, sub, … u Memory instructions: lw, sw u Branch instructions: beq 8

Instruction Memory l Instructions are bits l Programs are stored in memory u to be read or written just like data Processor Memory l Fetch & Execute Cycle u. Instructions are fetched and put into a special register u. Bits in the register "control" the subsequent actions u. Fetch the “next” instruction and continue Instructions/Data 9

Memory Organization l Viewed as a large, single-dimension array, with an address. 0 l A memory address is an index 1 into the array 2 3 l "Byte addressing" means that 4 the index points to a byte of 5 6 memory. . l Bytes are nice, but most data items use larger "words" l For MIPS, a word is 32 bits or 4 bytes. (We will discuss it later) 8 bits of data 8 bits of data 10

Registers vs. Memory l Arithmetic instructions operands must be registers, u only 32 registers provided l Compiler associates variables with registers l What about programs with lots of variables Control Input Memory Datapath Processor Output I/O 11

MIPS Registers l CPU u 32 -bit general purpose registers -GPRS (r 0 -r 31) u r 0 has fixed value of zero. Attempt to writing into r 0 is not illegal, but its value will not change; u Two 32 -bit registers – q Hi & Lo, hold results of integer multiply and divide u 32 -bit program counter - PC 12

MIPS Arithmetic l All instructions have 3 operands l Operand order is fixed (destination first) Example: C code: a = b + c MIPS ‘code’: add a, b, c “The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple” 13

MIPS Arithmetic l Design Principle: simplicity favors regularity. l Of course this complicates some things. . . C code: a = b + c + d; MIPS code: add a, b, c add a, a, d l Operands must be registers, only 32 registers provided l Each register contains 32 bits 14

How to Design a Processor: step-by-step l 1. Analyze instruction set architecture (ISA) ⇒ datapath requirements u meaning of each instruction is given by the data transfers (register transfers) u datapath must include storage element for ISA registers – datapath must support each data transfer l 2. Select set of datapath components and establish clocking methodology l 3. Assemble datapath meeting requirements l 4. Analyze implementation of each instruction to determine setting of control points that effects the data transfer. l 5. Assemble the control logic. 15

MIPS Instructions l The different fields are: u u u op: operation (“opcode”) of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of jump instruction 16

Instruction types l add, sub, or, slt uaddu rd, rs, rt u subu rd, rs, rt l lw, sw ulw rt, rs, imm 16 usw rt, rs, imm 16 l beq ubeq rs, rt, imm 16 17

MIPS Instructions (More Details) l 32 -bit fixed format instruction and 3 formats; u Register register and register u immediate computational instructions; u l single address mode for load/store instructions: u register content + offset (called base addressing); • simple branch conditions; branch instructions use PC relative addressing; u branch address = [PC] + 4×offset u • jump instructions with: 28 -bit addresses (jumps inside 256 megabyte regions), u absolute 32 -bit addresses. u 18

Register Transfer Descriptions l All start with instruction fetch: l {op , rs , rt , rd , shamt , funct} ← IMEM[ PC ] OR l {op , rs , rt , Imm 16} ← IMEM[ PC ] THEN 19

Microarchitecture l Multiple implementations for a single architecture: u. Single-cycle q Each instruction executes in a single clock cycle. u Multicycle q Each instruction is broken up into a series of shorter steps with one step per clock cycle. u Pipelined (variant on “multicycle”) q Each instruction is broken up into a series of steps with one step per clock cycle q Multiple instructions execute at once. 20

CPU clocking l Single Cycle CPU: All stages of an instruction are completed within one long clock cycle. The clock cycle is made sufficient long to allow each instruction to complete all stages without interruption and within one cycle. u 21

CPU Clocking l Multiple-cycle CPU: Only one stage of instruction per clock cycle. u. The clock is made as long as the slowest stage 22

References l http: //wwwinst. eecs. berkeley. edu/~cs 150/sp 12/agenda/l ec/lec 07 -MIPS. pdf l https: //web. cse. ohiostate. edu/~crawfis. 3/cse 67502/Slides/CSE 675_02 a_MIPS-ISA. pdf l https: //en. wikipedia. org/wiki/MIPS_architectur e 23

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