EEL 4712 Digital Design MIPS Processor Performance Processor

















- Slides: 17

EEL 4712 Digital Design (MIPS Processor Performance)

Processor Performance l Program Execution Time = (#instructions)*(cycles/instruction)*(second s/cycle) = # instructions x CPI x TC 2

Single-Cycle Performance l TC is limited by the critical path (lw) 3

Single-Cycle Performance l Single-cycle critical path: u. Tc = tpcq_PC + tmem + max(t. RFread, tsext + tmux) + t. ALU +tmem + tmux + t. RFsetup l In most implementations, limiting paths are: umemory, ALU, register file. u. Tc = tpcq_PC + 2*tmem + t. RFread + tmux + t. ALU + t. RFsetup 4

Single-Cycle Performance Example 5

Single-Cycle Performance Example TC= tpcq_PC + 2 tmem + t. RFread + tmux + t. ALU + t. RFsetup = [30 + 2(250) + 150 + 25 + 200 + 20] ps = 925 ps 6

Single-Cycle Performance Example l For a program with 100 billion instructions executing on a singlecycle MIPS processor l Execution Time = # instructions x CPI x TC l = (100 × 109)(1)(925 × 10 -12 s) = = 92. 5 seconds 7

How to make the performance better?

Pipelined MIPS Processor l Temporal parallelism l Divide single-cycle processor into 5 stages: u. Fetch u. Decode u. Execute u. Memory u. Writeback l Add pipeline registers between stages 9

Single-Cycle vs. Pipelined Performance

Single-Cycle and Pipelined Datapath 11

Corrected Pipelined Datapath Write. Reg must arrive at the same time as Result 12

Pipelined Control l Same control unit as single-cycle processor Control delayed to proper pipeline stage 13

Pipeline Hazards l Occurs when an instruction depends on results from previous instruction that hasn’t completed. l Types of hazards: u. Data hazard: register value not written back to register file yet u. Control hazard: next instruction not decided yet (caused by branches) 14

Pipelining Abstraction 15

References l http: //wwwinst. eecs. berkeley. edu/~cs 150/sp 12/agenda/l ec/lec 07 -MIPS. pdf l https: //web. cse. ohiostate. edu/~crawfis. 3/cse 67502/Slides/CSE 675_02 a_MIPS-ISA. pdf l https: //en. wikipedia. org/wiki/MIPS_architectur e l http: //homepage. divms. uiowa. edu/~ghosh/60 16. 90. pdf 16

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