EECS 362 Group 2 Kevin Cheung Michael Glowacki

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EECS 362 Group 2: Kevin Cheung Michael Glowacki Alex Romine Dave Sexton

EECS 362 Group 2: Kevin Cheung Michael Glowacki Alex Romine Dave Sexton

Arithmetic Instructions n n n n ADDU SUBU MULTU DIVU n n rd, rs

Arithmetic Instructions n n n n ADDU SUBU MULTU DIVU n n rd, rs 1, rs 2 ADDI ADDUI SUBUI rd, rs 1, immediate

Arithmetic Instructions n n n n ADD SUB n n ADDU SUBU All instructions

Arithmetic Instructions n n n n ADD SUB n n ADDU SUBU All instructions in R-type format. ADD/SUB treat the contents of source registers as signed (two’s complement) integers. ADD/SUB generate arithmetic overflow when result of operations are (> 231 – 1) or (< -231). ADDU/SUBU treats contents in source registers as unsigned integers ADDU/SUBU do not generate arithmetic overflow.

Arithmetic Instructions n n n ADDI SUBI n n ADDUI SUBUI All instructions in

Arithmetic Instructions n n n ADDI SUBI n n ADDUI SUBUI All instructions in I-type format. 16 -bit immediate is extended to 32 -bit. Sign extended for ADDI/SUBI and zero extended for ADDUI/SUBUI.

Arithmetic Instructions n n n MULT DIV n n MULTU DIVU All instructions in

Arithmetic Instructions n n n MULT DIV n n MULTU DIVU All instructions in R-type format. Only use floating point registers. MULT/DIV treat contents in source register as signed integers and MULTU/DIVU treat them as unsigned integers.

Logical Instructions n n n AND OR XOR rd, rs 1, rs 2 rd,

Logical Instructions n n n AND OR XOR rd, rs 1, rs 2 rd, rs 1, immediate n ANDI ORI XORI n LHI rd, immediate n n

Logical Instructions n n LHI (Load High Immediate) Places 16 -bit immediate into the

Logical Instructions n n LHI (Load High Immediate) Places 16 -bit immediate into the most significant portion of the destination register and fills remaining portion of destination register with 0’s.

Branch n n BEQZ BNEZ n n BEQZ branches when rs 1 is 0.

Branch n n BEQZ BNEZ n n BEQZ branches when rs 1 is 0. BNEZ branches when rs 1 is not 0. BFPT BFPF n n rs 1, name BFPT branches when FPSR is 1. BFPF branches when FPSR is 0.

Reusable Components n n Can reuse most of the ALU with some modifications. SLL

Reusable Components n n Can reuse most of the ALU with some modifications. SLL shifter can be reused. 32 -bit MUX’s Register bank can be reused but needs to be expanded.

Discussion of Complications n Limits to pipelining: Hazards prevent next instruction from executing during

Discussion of Complications n Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle. – Structural hazards: HW cannot support this combination of instructions. – Data hazards: Instruction depends on result of prior instruction still in the pipeline. – Control hazards: Pipelining of branches & other instructions that change the PC.