EE 447547 VLSI Design Lecture 9 Sequential Circuits

EE 447/547 VLSI Design Lecture 9: Sequential Circuits VLSI Design EE 447/547 Sequential circuits 1

Outline n n n n Floorplanning Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking VLSI Design EE 447/547 Sequential circuits 2

Project Strategy n Proposal q n Floorplan q q q n Begins with block diagram Annotate dimensions and location of each block Requires detailed paper design Schematic q n Specifies inputs, outputs, relation between them Make paper design simulate correctly Layout q Physical design, DRC, NCC, ERC VLSI Design EE 447/547 Sequential circuits 3

Floorplan n How do you estimate block areas? q q n Begin with block diagram Each block has n Inputs n Outputs n Function (draw schematic) n Type: array, datapath, random logic Estimation depends on type of logic VLSI Design EE 447/547 Sequential circuits 4

MIPS Floorplan VLSI Design EE 447/547 Sequential circuits 5

Area Estimation n Arrays: q q q n Datapaths q q q n Layout basic cell Calculate core area from # of cells Allow area for decoders, column circuitry Sketch slice plan Count area of cells from cell library Ensure wiring is possible Random logic q Compare complexity do a design you have done VLSI Design EE 447/547 Sequential circuits 6

MIPS Slice Plan VLSI Design EE 447/547 Sequential circuits 7

Typical Layout Densities n n n Typical numbers of high-quality layout Derate by 2 for class projects to allow routing and some sloppy layout. Allocate space for big wiring channels Element Area Random logic (2 metal layers) 1000 -1500 l 2 / transistor Datapath 250 – 750 l 2 / transistor Or 6 WL + 360 l 2 / transistor SRAM 1000 l 2 / bit DRAM 100 l 2 / bit ROM 100 l 2 / bit VLSI Design EE 447/547 Sequential circuits 8

Sequencing n Combinational logic q n output depends on current inputs Sequential logic q q output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline VLSI Design EE 447/547 Sequential circuits 9

Sequencing Cont. n n If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable q q n n Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high q Delay fast tokens so they don’t catch slow ones. VLSI Design EE 447/547 Sequential circuits 10

Sequencing Overhead n n n Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay q n Called sequencing overhead Some people call this clocking overhead q q But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence VLSI Design EE 447/547 Sequential circuits 11

Sequencing Elements n Latch: Level sensitive q n Flip-flop: edge triggered q n a. k. a. transparent latch, D latch A. k. a. master-slave flip-flop, D register Timing Diagrams q q q Transparent Opaque Edge-trigger VLSI Design EE 447/547 Sequential circuits 12

Sequencing Elements n Latch: Level sensitive q n Flip-flop: edge triggered q n a. k. a. transparent latch, D latch A. k. a. master-slave flip-flop, D register Timing Diagrams q q q Transparent Opaque Edge-trigger VLSI Design EE 447/547 Sequential circuits 13

Latch Design n n Pass Transistor Latch Pros + + n Cons q q q VLSI Design EE 447/547 Sequential circuits 14

Latch Design n n Pass Transistor Latch Pros + Tiny + Low clock load n Cons q q q Used in 1970’s Vt drop nonrestoring backdriving output noise sensitivity dynamic diffusion input VLSI Design EE 447/547 Sequential circuits 15

Latch Design n Transmission gate + - VLSI Design EE 447/547 Sequential circuits 16

Latch Design n Transmission gate + No Vt drop - Requires inverted clock VLSI Design EE 447/547 Sequential circuits 17

Latch Design n Inverting buffer + + + Fixes either n n q VLSI Design EE 447/547 Sequential circuits 18

Latch Design n Inverting buffer + Restoring + No backdriving + Fixes either n Output noise sensitivity n Or diffusion input q Inverted output VLSI Design EE 447/547 Sequential circuits 19

Latch Design n Tristate feedback + q VLSI Design EE 447/547 Sequential circuits 20

Latch Design n n Tristate feedback + Static q Backdriving risk Static latches are now essential VLSI Design EE 447/547 Sequential circuits 21

Latch Design n Buffered input + + VLSI Design EE 447/547 Sequential circuits 22

Latch Design n Buffered input + Fixes diffusion input + Noninverting VLSI Design EE 447/547 Sequential circuits 23

Latch Design n Buffered output + VLSI Design EE 447/547 Sequential circuits 24

Latch Design n Buffered output + No backdriving n Widely used in standard cells + Very robust (most important) Rather large Rather slow (1. 5 – 2 FO 4 delays) High clock loading VLSI Design EE 447/547 Sequential circuits 25

Latch Design n Datapath latch + - VLSI Design EE 447/547 Sequential circuits 26

Latch Design n Datapath latch + Smaller, faster - unbuffered input VLSI Design EE 447/547 Sequential circuits 27

Flip-Flop Design n Flip-flop is built as pair of back-to-back latches VLSI Design EE 447/547 Sequential circuits 28

Enable n Enable: ignore clock when en = 0 q q Mux: increase latch D-Q delay Clock Gating: increase en setup time, skew VLSI Design EE 447/547 Sequential circuits 29

Reset n n Force output low when reset asserted Synchronous vs. asynchronous VLSI Design EE 447/547 Sequential circuits 30

Set / Reset n n Set forces output high when enabled Flip-flop with asynchronous set and reset VLSI Design EE 447/547 Sequential circuits 31

Sequencing Methods n n n Flip-flops 2 -Phase Latches Pulsed Latches VLSI Design EE 447/547 Sequential circuits 32

Timing Diagrams Contamination and Propagation Delays tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tpcq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time VLSI Design EE 447/547 Sequential circuits 33

Max-Delay: Flip-Flops VLSI Design EE 447/547 Sequential circuits 34

Max-Delay: Flip-Flops VLSI Design EE 447/547 Sequential circuits 35

Max Delay: 2 -Phase Latches VLSI Design EE 447/547 Sequential circuits 36

Max Delay: 2 -Phase Latches VLSI Design EE 447/547 Sequential circuits 37

Max Delay: Pulsed Latches VLSI Design EE 447/547 Sequential circuits 38

Max Delay: Pulsed Latches VLSI Design EE 447/547 Sequential circuits 39

Min-Delay: Flip-Flops VLSI Design EE 447/547 Sequential circuits 40

Min-Delay: Flip-Flops VLSI Design EE 447/547 Sequential circuits 41

Min-Delay: 2 -Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! VLSI Design EE 447/547 Sequential circuits 42

Min-Delay: 2 -Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! VLSI Design EE 447/547 Sequential circuits 43

Min-Delay: Pulsed Latches Hold time increased by pulse width VLSI Design EE 447/547 Sequential circuits 44

Min-Delay: Pulsed Latches Hold time increased by pulse width VLSI Design EE 447/547 Sequential circuits 45

Time Borrowing n In a flop-based system: q q q n Data launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system q q q Data can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle VLSI Design EE 447/547 Sequential circuits 46

Time Borrowing Example VLSI Design EE 447/547 Sequential circuits 47

How Much Borrowing? 2 -Phase Latches Pulsed Latches VLSI Design EE 447/547 Sequential circuits 48

Clock Skew n n We have assumed zero clock skew Clocks really have uncertainty in arrival time q q q Decreases maximum propagation delay Increases minimum contamination delay Decreases time borrowing VLSI Design EE 447/547 Sequential circuits 49

Skew: Flip-Flops VLSI Design EE 447/547 Sequential circuits 50

Skew: Latches 2 -Phase Latches Pulsed Latches VLSI Design EE 447/547 Sequential circuits 51

Two-Phase Clocking n n n If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important q n n No tools to analyze clock skew An easy way to guarantee hold times is to use 2 phase latches with big nonoverlap times Call these clocks f 1, f 2 (ph 1, ph 2) VLSI Design EE 447/547 Sequential circuits 52

Safe Flip-Flop n In class, use flip-flop with nonoverlapping clocks q q n Very slow – nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer q Add buffers to slow signals if hold time is at risk VLSI Design EE 447/547 Sequential circuits 53

Summary n Flip-Flops: q n 2 -Phase Transparent Latches: q n Very easy to use, supported by all tools Lots of skew tolerance and time borrowing Pulsed Latches: q Fast, some skew tol & borrow, hold time risk VLSI Design EE 447/547 Sequential circuits 54