EE 143 F 2010 Lecture 19 CMOS Inverter

EE 143 F 2010 Lecture 19 CMOS Inverter Layout P-well mask (dark field) VDD PMOS W/L=9 l/2 l Gate (clear field) Note body contacts: • p-well to GND Select mask (dark field & clear field) • n-substrate to VDD NMOS W/L=3 l/2 l GND Professor N Cheung, U. C. Berkeley Active (clear field) Contact (dark field) Metal (clear field)

EE 143 F 2010 Lecture 19 Visualizing Layouts and Cross-Sections with SIMPLer SIMPL is a CAD tool created by Prof. Neureuther’s group • allows IC designers to visualize device cross-sections corresponding to a fabrication process and physical layout. A Berkeley undergraduate student, Harlan Hile, created a mini-version of SIMPL (called SIMPLer) for EE 40. • It’s a JAVA program -> can be run on any computer, as well as on a web server. • A 3 D version SIMPL-GL can be accessed at http: //cuervo 2. eecs. berkeley. edu/Volcano/simpl_gl/main. htm Professor N Cheung, U. C. Berkeley

EE 143 F 2010 Professor N Cheung, U. C. Berkeley Lecture 19

EE 143 F 2010 Professor N Cheung, U. C. Berkeley Lecture 19

EE 143 F 2010 Professor N Cheung, U. C. Berkeley Lecture 19

EE 143 F 2010 Professor N Cheung, U. C. Berkeley Lecture 19

EE 143 F 2010 Professor N Cheung, U. C. Berkeley Lecture 19

EE 143 F 2010 Lecture 19 Twin Well + STI CMOS Process Define active areas; etch Si trenches Fill trenches (deposit Si. O 2 then CMP) Form wells (implantation + thermal anneal) Grow gate oxide Deposit poly-Si and pattern gate electrodes Implant source/drain and body-contact regions Activate dopants (thermal anneal) Deposit insulating layer (Si. O 2); planarize (CMP) Open contact holes; deposit & pattern metal layer Professor N Cheung, U. C. Berkeley

EE 143 F 2010 Lecture 19 3 D view of a CMOS inverter after contact etch. Professor N Cheung, U. C. Berkeley 9

EE 143 F 2010 Lecture 19 Well Engineering P-tub N-tub Twin Tub Professor N Cheung, U. C. Berkeley 10

EE 143 F 2010 Lecture 19 Twin Well CMOS Process Flow Professor N Cheung, U. C. Berkeley 11

EE 143 F 2010 Lecture 19 Retrograde Well - formed by high energy (>200 ke. V) implantation C(x) Conventional well (depth and profile controlled by diffusion drive-in) Retrograde well (depth and profile controlled by implantation energy and dose) x Professor N Cheung, U. C. Berkeley 12

EE 143 F 2010 Lecture 19 Conventional vs Retrograde Well 1) Very low thermal budget for well formation (no need for diffusion drive-in) 2) Retrograde Well is formed AFTER field oxidation small lateral diffusion and localized high conc under FOX Professor N Cheung, U. C. Berkeley 13

EE 143 F 2010 Lecture 19 Example: Formation of Channel Stop and Retrograde Well in a single step Channel stop Professor N Cheung, U. C. Berkeley Retrograde well 14

EE 143 F 2010 Lecture 19 Multiple Implants for Well Engineering Professor N Cheung, U. C. Berkeley 15

EE 143 F 2010 Lecture 19 Channel Engineering Shallow Oxide Trench Isolation Professor N Cheung, U. C. Berkeley 16 N Cheung EE 243 S

EE 143 F 2010 Lecture 19 Generic Silicon-on-Insulator (SOI) CMOS Process Flow Professor N Cheung, U. C. Berkeley 17

EE 143 F 2010 Lecture 19 SOI Process Flow (continued) Professor N Cheung, U. C. Berkeley 18

EE 143 F 2010 Lecture 19 Self-Aligned Channel V-gate by Optical Lithography (SALVO) Process Smallest feature printable by lithography Oxide spacer poly-Si gate CVD oxide n+ Si. O 2 Ti. Si 2 Professor N Cheung, U. C. Berkeley Normal S/D implant CVD oxide n+ n+ n+ Angled Thermal Implant gate oxide n+ pocket * Sub-50 nm channels 19

EE 143 F 2010 Lecture 19 SALVO Process Flow or See Homework Problem Chang et al, IEDM 2000 Professor N Cheung, U. C. Berkeley 20

EE 143 F 2010 Lecture 19 SUMMARY OF IC PROCESS INTEGRATION MODULE • Self aligned techniques: channel stop, Source/Drain, LDD, SALICIDE • How to read process flow descriptions and cross-sections • Generic NMOS Process with LOCOS • Generic CMOS Process with LOCOS and single well • Modified Processes: • Shallow Trench Isolation (STI), Twin Wells, Retrograde Well, SOI CMOS Professor N Cheung, U. C. Berkeley 21