EE 141 Project 32 x 32 SRAM Abhinav

EE 141 Project: 32 x 32 SRAM Abhinav Gupta, Glen Wong Optimization goals: • Balance between area and performance • Minimize area without sacrificing performance

SRAM Cell Design • 6 -T SRAM Cell • Modified provided SRAM cell to decrease area from 38. 08μm 2 to 31. 68μm 2. • Inverter PMOS: 0. 36μm • Inverter NMOS: 1. 08μm • Pass Transistor: 0. 54μm

Read and Write Noise Margins Read Noise Margin Analysis • Read Voltage Rise: 284 m. V Write Noise Margin Analysis • Write Cell Voltage: 181 m. V

Decoder Design • Each input to the Decoder was buffered via inverters due to branching. • The split SRAM allows for reduced Cfixed. • The decreased size of SRAM cell enables lower load capacitance. • Calculated Delay: 624. 65 ps

Decoder Implementation • Layout of final Decode Stage on the left consists of 3 inputs and 1 output. • Simulated delay of full decoder: 547. 51 ps

Adder Design • Ripple-Carry Adder Chain • Produces both Sum and its complement values • Critical Path consists of initial carry generation to evaluation of MSB sum value • Calculated Delay: 690. 5 ps

Adder Implementation • Layout of Full Adder consists of 16 inputs and 10 outputs and is directly connected to the pre-decode stage. • Simulated delay of full decoder: 886. 94 ps

SRAM Array Design • Split SRAM Array to save wire capacitance between predecode and final-decode stages. • Reduced SRAM Cell Size without decreasing transistor sizes • Minimizing area of cell, and decode stage without affecting delay/performance.

SRAM Array Layout • Pre-Charge Devices only one side of SRAM (other side internally connected). • Output Buffers only on one side of SRAM as well. • Total Simulated Delay: 1. 539 ns • Overall Area: 49, 607μm 2.