Edward Jezisek Brandon Autrey Edward Nowlin Renato Ortega

Edward Jezisek Brandon Autrey Edward Nowlin Renato Ortega Group 2

Motivation • To improve the quality of ECG signals acquired from patients in an MRI environment • ECG quality in MRI machines is lacking • Current filter selection is confusing • Current filters are imperfect • New MRI scans create problems

Objectives • To further the use of adaptive algorithms in medical practice • Make patient monitors easier to use • Improve the quality of ECG Signals

Specifications and Requirements Component Requirement/Specification DAC 1 k. Hz (Diagnostic Quality) 3 Parallel Pins ADC 50 k. Hz (Diagnostic Quality) 6 Parallel Pins Processor Obtain Data, Perform the LMS and Output data at 150 k. Hz

Noise Contributions • Electrical interference from power lines add 50 or 60 Hz power-line frequency. • Muscle contraction and muscle activity can generate high frequency electromyography (EMG) noise. • Motion artifacts such as movement of the electrode over the skin surface.

Overall System Diagram

Hardware

PCB Layout • 417 components • 6 layers • Digital and Analog ground plane • ESD/Defibrillation protection • Front end amplification and filtering • 4 ECG inputs and outputs • 3 gradient antenna inputs • ARM Cortex M 4 Processor

Digital to Analog Converter (AD 5640) • 14 Bit conversion resolution • Single channel • 3 wire serial interface • Clock rate up to 30 MHz

ARM Cortex M 4 F • RISC based microprocessor • 80 MHz clock speed • Two 12 -bit ADC modules with maximum sample rate of 1 MSPS • 256 KB Flash memory • Four SSI Modules • 105 GPIOs including 24 shared analog input channels • Single-precision Floating Point Unit (FPU)

PCB Schematic

Input from each ECG lead • Removed because of NDA

Input from each gradient antenna • Removed because of NDA

ESD/Defibrillation Protection • In a situation when a patient goes into heart failure, a defibrillator may need to be utilized • A SG 75 gas discharge tube is used to short the current going into the filter when voltage exceeds 75 V • Clamping diodes are also used after the discharge tube to short the circuit then the voltage exceeds +/-3. 3 V

ESD/Defibrillation Protection • Removed because of NDA

Sallen Key Filter • Front end filtering is used to eliminate as much interference as possible before the analog signal is converted into a digital signal • The Sallen key filter has a cut off of about 5500 rad/s or 9 k. Hz

3 rd order Sallen key filter • Removed because of NDA

Op amp biasing and gain • Op amp is biased to 1. 2 V to allow for properation of the analog to digital converter. • Biasing is achieved through the use of applying a voltage to the circuit and using a voltage divider • The Op amp circuit is configured to have a gain of 1. 5

Op amp biasing and gain Removed because of NDA Op amp biasing Gain

PCB Power • Analog and Digital ground planes are separated by a CLC filter • Input voltage is 5 V • Voltage reference is used to step voltage down to 3 V for applicable components • Linear regulators are used to maintain a steady voltage • Digital and Analog grounds are separated by a CLC filter

PCB Power • Removed because of NDA

Printed Circuit Board

Software

Linear Filters • Pros: • • Easier to make, and is already implemented in many machines Is possible to implement with an analog system(few or no extra parts) Quick and usable for diagnostic quality devices Cheaper • Cons: • Requires a professional to select the correct linear filter • Easy to make mistakes; if a mistake is made that can be costly in terms of receiving useless data. And in the medical profession; time is of the essence. • Training is confusing • Quality is lacking

Adaptive Filters • Pros: • Much better quality • Less input data from user • Cons: • Difficulties filtering the incoming amount of data • More research is required for a full implementation of it • Costs more (R&D)

Least Mean Square Filter Example

Real-Time Matlab Plot • Video removed due to file size limitations

Important Data Points

Analog to Digital Converter • Two ADC modules that use Successive Approximation Register (SAR) architecture to deliver low-power 12 -bit conversion resolution • Supports 24 input channels • Maximum sampling speed of 1 million samples per second • Four programmable sample conversion sequencers • ADC logic runs at 16 MHz • 3. 3 V reference voltage

Programmable Sequencers • We used sequencer SS 0 is used to sample 6 signals at once • 3 ECG signals • 3 Gradient signals • Sample sequencer is triggered by processor interrupt Sequencer # of samples Depth of FIFO SS 3 1 1 SS 2 4 4 SS 1 4 4 SS 0 8 8

Synchronous Serial Interface (SSI) • Programmable data frame size from 4 and 16 bits • Transmit FIFO 16 bits wide and 8 locations deep • Master or slave operation • Three types of frame formats • MICROWIRE and Freescale SPI • FSS pin is active low for duration of frame transfer • Texas Instruments Synchronous Serial Interface • FSS pin is pulsed for one serial clock period prior to frame transmission • Three SSI modules used for the three DACs.

Continuous TI Synchronous Serial Frame Format

SPI Digital Data

Digital to Analog Converter • Single channel 3 -wire serial interface compatible with SPI • SYNC, SCLK, and DIN • Clock rate up to 30 MHz • Reference voltage of 2. 7 V AD 5660 AD 5640 Conversion resolution 16 -bit 14 -bit Input Shift Register 24 -bit 16 -bit

Write Sequence for DAC

DAC output of 1 KHz sine wave

Class Diagram

Testing Procedures

Functional Testing • MATLAB • Used to confirm the device sends the correct signal • Oscilloscope • Used to read the data from the PCB, ensures correct signals sent and received • Function Generator • Supplies various signals that were filtered with the LMS

ECG Generator

Connections

ECG Signal with No Filtering

ECG Signal with Adaptive Filtering • Video removed due to file size limitations

Issues • Noise of about +-30 m. V on the board • UART is not working on PCB • Difficulty selecting step size and filter order

Budget Parts Price Quantity Total Tiva C Series Dev. Board $200. 00 2 $400. 00 Analog to Digital Converter (ADS 8556 EVM) $101. 00 1 $101. 00 Components $1000 Varies $1, 000. 00 Circuit Board $750. 00 2 $1, 500. 00 PCB Assembly $2500. 00 1 $2, 500. 00 JTAG Programmer $79. 00 1 $79. 00 Total Costs $5, 580. 00 Total Budget $10, 000. 00 Extra Budget $4420. 00

Progress 120 100 80 60 40 20 0 Project Development Research PCB Completion Parts Acquisition Software Development Testing Total

Work Distribution Tasks Group Member Front End Design Edward Nowlin PCB Design and Layout Edward Nowlin and Renato Ortega Integration of PCB Brandon Autrey and Edward Jezisek Least Mean Squares Filter Edward Jezisek MATLAB Display Edward Jezisek and Brandon Autrey ADC Brandon Autrey DAC and SPI Edward Jezisek and Brandon Autrey

Questions?