ECS 154 B Computer Architecture Multicycle Controller Design

ECS 154 B Computer Architecture Multicycle Controller Design (Continued) http: //www. cs. ucdavis. edu/~erciyes/154 B 10/03/01 ©UCB Fall 2001

10/03/01 Operand Fetch Instruction Fetch PC Next PC Exec ©UCB Fall 2001 ° Place enables on all registers Reg. File Result Store Data Mem Access Mem. Wr Reg. Dst Reg. Wr Mem. Rd Mem. Wr ALUctr ALUSrc Ext. Op Equal n. PC_sel Partitioning the CPI=1 Datapath ° Add registers between smallest steps

10/03/01 Ext. Op Equal B ° Critical Path ? ©UCB Fall 2001 S Reg. File Reg. Dst Reg. Wr Mem. To. Reg Mem. Rd Mem. Wr ALUctr Ext ALUSrc ALU A Result Store Reg File Mem Access IR n. PC_sel E Data Mem Operand Fetch Instruction Fetch PC Next PC Recap: Example Multicycle Datapath M

Recap: FSM specification “instruction fetch” IR <= MEM[PC] 0000 “decode” A <= R[rs] B <= R[rt] R-type S <= A fun B 0100 ORi S <= A or ZX 0110 LW S <= A + SX 1000 M <= MEM[S] 1001 SW BEQ S <= A + SX 1011 MEM[S] <= B PC <= PC + 4 R[rd] <= S R[rt] <= M PC <= PC + 4 0101 10/03/01 0111 1010 ©UCB Fall 2001 1100 PC <= Next(PC) 0011 Write-back Memory Execute 0001

Sequencer-based control unit: Statemachine ++ Control Logic Multicycle Datapath Outputs Inputs 1 Adder Types of “branching” • Set state to 0 • Dispatch (state 1) • Use incremented state number State Reg Address Select Logic Opcode 10/03/01 ©UCB Fall 2001

Recap: Micro-controller Design ° The state digrams that arise define the controller for an instruction set processor are highly structured ° Use this structure to construct a simple “microsequencer” • Each state in previous diagram becomes a “microinstruction” • Microinstructions often taken sequentially ° Control reduces to programming this device sequencer datapath control microinstruction ( ) micro-PC 10/03/01 sequencer ©UCB Fall 2001

Recap: Specific Sequencer from last lecture °Sequencer-based control unit from last lecture • Called “micro. PC” or “µPC” vs. state register Control Value Effect 00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 1 Adder ROM: 10/03/01 R-type BEQ ori LW SW 000000 000100 001101 100011 101011 0100 0011 0110 1000 1011 µAddress Select Logic ©UCB Fall 2001 micro. PC Mux 2 1 0 0 ROM Opcode

Recap: Microprogram Control Specification µPC 0000 0001 0010 BEQ 0011 R: 0100 0101 ORi: 0110 0111 LW: Taken 0 1 10/03/01 x x inc zero x x inc zero 0 0 or 1 1 0 0 1000 SW: 1001 1010 1011 1100 Next IR PC Ops Exec Mem Write-Back en sel A B Ex Sr ALU S R W M M-R Wr Dst ? inc 1 0 load 1 inc x zero 1 1 x zero 1 0 x inc 0 1 fun 1 x zero 1 0 add 1 1 0 1 0 1 ©UCB Fall 2001 0 add 1 0 1

Recap: Overview of Control ° Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Sequencing Control Function Finite State Diagram Microprogram Explicit Next State + Dispatch ROMs Logic Representation Logic Equations Implementation Technique 10/03/01 PLA Microprogram counter Truth Tables ROM “hardwired control” ©UCB Fall 2001 “microprogrammed control”

The Big Picture: Where are We Now? ° The Five Classic Components of a Computer Processor Input Control Memory Datapath Output ° Today’s Topics: • • 10/03/01 Microprogramed control Administrivia Microprogram it yourself Exceptions ©UCB Fall 2001

Microprogramming (Maurice Wilkes) ° Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance 10/03/01 ©UCB Fall 2001

“Macroinstruction” Interpretation Main Memory ADD SUB AND . . . DATA execution unit CPU User program plus Data this can change! one of these is mapped into one of these AND microsequence control memory e. g. , Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) 10/03/01 ©UCB Fall 2001

Variations on Microprogramming ° “Horizontal” Microcode – control field for each control point in the machine µseq µaddr A-mux B-mux bus enables register enables ° “Vertical” Microcode – compact microinstruction format for each class of microoperation – local decode to generate all control points (remember ALU? ) branch: µseq-op µadd execute: ALU-op A, B, R memory: mem-op S, D Horizontal Vertical 10/03/01 ©UCB Fall 2001

Extreme Horizontal 3 1. . . N 3 N 2 N 1 N 0 1 bit for each loadable register enb. MAR enb. AC. . . input select Incr PC ALU control Depending on bus organization, many potential control combinations simply wrong, i. e. , implies transfers that can never happen at the same time. Makes sense to encode fields to save ROM space Example: mem_to_reg and ALU_to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bits NOTE: the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction 10/03/01 ©UCB Fall 2001

More Vertical Format src dst D E C other control fields next states inputs D E C MUX Some of these may have nothing to do with registers! Multiformat Microcode: 6 1 3 0 cond 1 1 3 dst D E C 10/03/01 next address 3 src 3 alu Branch Jump Register Xfer Operation D E C ©UCB Fall 2001

Hybrid Control Not all critical control information is derived from control logic E. g. , Instruction Register (IR) contains useful control information, such as register sources, destinations, opcodes, etc. enable signals from control IR op to control 10/03/01 R S 2 R D D E C rs 1 rs 2 rd ©UCB Fall 2001 Register File

Vax Microinstructions VAX Microarchitecture: 96 bit control store, 30 fields, 4096 µinstructions for VAX ISA encodes concurrently executable "microoperations" 95 87 84 USHF 001 = left 010 = right. . . 101 = left 3 68 65 63 11 UALU USUB 010 = A-B-1 100 = A+B+1 ALU Control UJMP 00 = Nop 01 = CALL 10 = RTN Jump Address Subroutine Control ALU Shifter Control Current intel architecture: 80 -bit microcode, 8192 instructions 10/03/01 ©UCB Fall 2001 0

Horizontal vs. Vertical Microprogramming NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal Vertical + more control over the potential parallelism of operations in the datapath + easier to program, not very different from programming a RISC machine in assembly language - uses up lots of control store 10/03/01 - ©UCB Fall 2001 extra level of decoding may slow the machine down

How Effectively are we utilizing our hardware? IR <- Mem[PC] A <- R[rs]; B<– R[rt] S <– A + B R[rd] <– S; PC <– PC+4; S <– A or ZX R[rt] <– S; PC <– PC+4; S <– A + SX M <– Mem[S] <- B R[rd] <– M; PC <– PC+4; PC < PC+SX; ° Example: memory is used twice, at different times • Ave mem access per inst = 1 + Flw + Fsw ~ 1. 3 • if CPI is 4. 8, imem utilization = 1/4. 8, dmem =0. 3/4. 8 ° We could reduce HW without hurting performance 10/03/01 • extra control ©UCB Fall 2001

“Princeton” Organization A-Bus B Bus next PC P C IR ZX SX Reg File A B S Mem W-Bus ° Single memory for instruction and data access • memory utilization -> 1. 3/4. 8 ° Sometimes, muxes replaced with tri-state buses • Difference often depends on whether buses are internal to chip (muxes) or external (tri-state) ° In this case our state diagram does not change • several additional control signals • must ensure each bus is only driven by one source on each cycle 10/03/01 ©UCB Fall 2001

Today: Alternative datapath (book) ° Miminizes Hardware: 1 memory, 1 adder PCWr. Cond Zero Mem. Wr IRWr Reg. Dst ALUSel. A Reg. Wr 32 PC 32 32 5 Rt 0 Rd Ra Rb Reg File Rw bus. W bus. B 1 1 Mux 0 Imm 16 Extend Ext. Op 10/03/01 bus. A A ©UCB Fall 2001 1 4 B << 2 32 32 0 1 32 32 2 3 32 Memto. Reg Zero ALU Control ALUOp ALUSel. B ALU Out Wr. Adr 32 Din Dout 32 Rt Mux Ideal Memory 1 5 32 ALU 32 Rs Mem Data Reg Mux RAdr 0 Mux 0 32 Instruction Reg 32 1 Mux Ior. D PCSrc

New Finite State Machine (FSM) Spec IR <= MEM[PC] “instruction fetch” PC <= PC + 4 0000 “decode” Q: How improve to do something in state 0001? 0001 ALUout <= A fun B 0100 ORi ALUout <= A or ZX 0110 LW ALUout <= A + SX 1000 M <= MEM[ALUout] 1001 R[rd] <= ALUout 0101 10/03/01 R[rt] <= ALUout 0111 BEQ SW ALUout <= A + SX 1011 MEM[ALUout] <= B R[rt] <= M 1010 ©UCB Fall 2001 1100 ALUout <= PC +SX 0010 If A = B then PC <= ALUout 0011 Memory Write-back Execute R-type

Finite State Machine (FSM) Spec IR <= MEM[PC] “instruction fetch” PC <= PC + 4 0000 ALUout <= PC +SX “decode” 0001 ALUout <= A fun B 0100 ORi ALUout <= A or ZX 0110 LW ALUout <= A + SX 1000 M <= MEM[ALUout] 1001 R[rd] <= ALUout 0101 10/03/01 R[rt] <= ALUout 0111 BEQ SW ALUout <= A + SX 1011 MEM[ALUout] <= B R[rt] <= M 1010 ©UCB Fall 2001 1100 If A = B then PC <= ALUout 0010 Memory Write-back Execute R-type

Designing a Microinstruction Set 1) Start with list of control signals 2) Group signals together that make sense (vs. random): called “fields” 3) Place fields in some logical order (e. g. , ALU operation & ALU operands first and microinstruction sequencing last) 4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals • Use computers to design computers 5) To minimize the width, encode operations that will never be used at the same time 10/03/01 ©UCB Fall 2001

Multiple Bit Control Single Bit Control 1&2) Start with list of control signals, grouped into fields Signal name Effect when deasserted Effect when asserted ALUSel. A 1 st ALU operand = PC 1 st ALU operand = Reg[rs] Reg. Write None Reg. is written Memto. Reg. write data input = ALU Reg. write data input = memory Reg. Dst Reg. dest. no. = rd Mem. Read None Memory at address is read, MDR <= Mem[addr] Mem. Write None Memory at address is written Ior. D Memory address = PC Memory address = S IRWrite None IR <= Memory PCWrite None PC <= PCSource PCWrite. Cond None IF ALUzero then PC <= PCSource = ALUout Ext. Op Zero Extended Signal name Value ALUOp 00 01 10 11 ALUSel. B 00 01 10 11 10/03/01 Effect ALU adds ALU subtracts ALU does function code ALU does logical OR 2 nd ALU input = 4 2 nd ALU input = Reg[rt] 2 nd ALU input = extended, shift left 2 2 nd ALU input = extended ©UCB Fall 2001

Start with list of control signals, cont’d ° For next state function (next microinstruction address), use Sequencer-based control unit from last lecture • Called “micro. PC” or “µPC” vs. state register Signal Value Sequen -cing 01 10 Effect 1 00 Next µaddress = dispatch ROM Next µaddress = µaddress + 1 Adder ° Could even include “branch” option which changes micro. PC by adding offset when certain control signals are true. 10/03/01 ©UCB Fall 2001 µAddress Select Logic micro. PC Mux 2 1 0 0 ROM Opcode

3) Microinstruction Format: unencoded vs. encoded fields Field Name Width Control Signals Set wide narrow ALU Control 4 2 ALUOp SRC 1 2 1 ALUSel. A SRC 2 5 3 ALUSel. B, Ext. Op ALU Destination 3 2 Memory 2 Mem. Read, Mem. Write, Ior. D Memory Register 1 1 IRWrite PCWrite Control PCSource 3 2 PCWrite, PCWrite. Cond, Sequencing 3 2 Addr. Ctl Total width 24 15 bits 10/03/01 3 Reg. Write, Memto. Reg, Reg. Dst ©UCB Fall 2001

4) Legend of Fields and Symbolic Names Field Name Values for Field Function of Field with Specific Value ALU Add ALU adds Subt. ALU subtracts Func code ALU does function code Or ALU does logical OR SRC 1 PC 1 st ALU input = PC rs 1 st ALU input = Reg[rs] SRC 2 4 2 nd ALU input = 4 Extend 2 nd ALU input = sign ext. IR[15 -0] Extend 0 2 nd ALU input = zero ext. IR[15 -0] Extshft 2 nd ALU input = sign ex. , sl IR[15 -0] rt 2 nd ALU input = Reg[rt] destination rd ALU Reg[rd] = ALUout rt ALU Reg[rt] = ALUout rt Mem Reg[rt] = Memory Read PC Read memory using PC Read ALU Read memory using ALUout for addr Write ALU Write memory using ALUout for addr Memory register IR IR = Mem PC write ALU PC = ALUout. Cond IF ALU Zero then PC = ALUout Sequencing Seq Go to sequential µinstruction Fetch Go to the first microinstruction Dispatch using ROM. 10/03/01 ©UCB Fall 2001

Quick check: what do these fieldnames mean? Destination: Code Name 00 01 10 11 Reg. Write --0 rd ALU 1 rt MEM 1 Mem. To. Reg X X 0 1 0 SRC 2: Code 000 001 010 011 100 111 10/03/01 Name --4 rt Ext. Shft Extend 0 ALUSel. B X 00 01 10 11 11 Ext. Op X X X 1 1 0 ©UCB Fall 2001 Reg. Dest

Alternative datapath (book): Multiple Cycle Datapath ° Miminizes Hardware: 1 memory, 1 adder PCWr. Cond Zero Mem. Wr IRWr Reg. Dst ALUSel. A Reg. Wr 32 PC 32 32 5 Rt 0 Rd Ra Rb Reg File Rw bus. W bus. B 1 1 Mux 0 Imm 16 Extend Ext. Op 10/03/01 bus. A A ©UCB Fall 2001 1 4 B << 2 32 32 0 1 32 32 2 3 32 Memto. Reg Zero ALU Control ALUOp ALUSel. B ALU Out Wr. Adr 32 Din Dout 32 Rt Mux Ideal Memory 1 5 32 ALU 32 Rs Mem Data Reg Mux RAdr 0 Mux 0 32 Instruction Reg 32 1 Mux Ior. D PCSrc

Microprogram it yourself! Label ALU SRC 1 Sequencing SRC 2 Fetch: Add Seq 4 10/03/01 PC ALU Dest. Memory Mem. Reg. Read PC ©UCB Fall 2001 PC Write IR ALU

Microprogram it yourself! Label ALU SRC 1 Sequencing SRC 2 Fetch: Add Seq Add PC 4 PC Extshft Dispatch rs rt Seq Fetch Rtype: Func Dest. Memory Mem. Reg. PC Write Read PC ALU rd ALU Ori: Or Seq rs Extend 0 rt ALU Lw: Add rs IR Fetch Extend Seq Read ALU Seq rt MEM Sw: Add rs Fetch Extend Seq Write ALU 10/03/01 Fetch ©UCB Fall 2001

Legacy Software and Microprogramming ° IBM bet company on 360 Instruction Set Architecture (ISA): single instruction set for many classes of machines • (8 -bit to 64 -bit) ° Stewart Tucker stuck with job of what to do about software compatibility ° If microprogramming could easily do same instruction set on many different microarchitectures, then why couldn’t multiple microprograms do multiple instruction sets on the same microarchitecture? ° Coined term “emulation”: instruction set interpreter in microcode for non-native instruction set ° Very successful: in early years of IBM 360 it was hard to know whether old instruction set or new instruction set was more frequently used 10/03/01 ©UCB Fall 2001

Microprogramming Pros and Cons ° Ease of design ° Flexibility • Easy to adapt to changes in organization, timing, technology • Can make changes late in design cycle, or even in the field ° Can implement very powerful instruction sets (just more control memory) ° Generality • Can implement multiple instruction sets on same machine. • Can tailor instruction set to application. ° Compatibility • Many organizations, same instruction set ° Costly to implement ° Slow 10/03/01 ©UCB Fall 2001

An Alternative Multi. Cycle Data. Path A-Bus B Bus next PC P C inst mem IR ZX SX Reg File A B S mem W-Bus ° In each clock cycle, each Bus can be used to transfer from one source ° µ-instruction can simply contain B-Bus and W-Dst fields 10/03/01 ©UCB Fall 2001

What about a 2 -Bus Microarchitecture (datapath)? Instruction Fetch A-Bus B Bus next PC P C IR ZXSX Reg File A S B Mem M Decode / Operand Fetch next PC 10/03/01 P C IR ZXSX Reg File A B ©UCB Fall 2001 S Mem M

Load Execute next PC P C IR ZXSX Reg File A B S Mem M Mem next PC P C IR ZXSX Reg File A B S addr Mem M S Mem M Write-back next PC ZXSX B ° What about 1 bus ? 1 adder? 1 Register port? ©UCB Fall 2001 10/03/01

Summary ° Specialize state-diagrams easily captured by microsequencer • simple increment & “branch” fields • datapath control fields ° Most microprogramming-based controllers vary between: • horizontal organization (1 control bit per control point) • vertical organization (fields encoded in the control memory and must be decoded to control something) ° Steps: • identify control signals, group them, develop “mini language”, then microprogram ° Control design reduces to Microprogramming • Arbitrarily complicated instructions possible 10/03/01 ©UCB Fall 2001

Summary: Microprogramming one inspiration for RISC ° If simple instruction could execute at very high clock rate… ° If you could even write compilers to produce microinstructions… ° If most programs use simple instructions and addressing modes… ° If microcode is kept in RAM instead of ROM so as to fix bugs … ° If same memory used for control memory could be used instead as cache for “macroinstructions”… ° Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine? 10/03/01 ©UCB Fall 2001