ECE 565 VLSI Design Automation Introduction VLSI Design

ECE 565: VLSI Design Automation Introduction: VLSI Design Flow & Logic Opt. /Tech. Mapping Shantanu Dutt ECE Dept. UIC Acknowledegements: Some slides are from publicly available slides by Naveed Sherwani (VLSI design flow) and S. Devadas (logic opt. )

Opt. metrics: -- Speed -- Power -- WL/area Other metrics (constraints): -- Temperature -- temperature

IC Design Steps (cont. ) Specifications High-level Description Functional Description Behavioral VHDL, C Structural VHDL Figs. [©Sherwani]

IC Design Steps (cont. ) High-level Description Specifications Physical Design Placed & Routed Design Packaging Synthesis Technology Mapping Gate-level Design Fabrication Functional Description HLS Logic Description X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [©Sherwani]

RTL Design Flow HDL Includes HLS manual design RTL Synthesis Library/ module generators netlist logic optimization netlist a 0 b 1 s a 0 b 1 d s q clk Logic opt. + Technology mapping Circuit resynthesis physical (e. g. , buff. Ins. , design cell replication) layout d

Logic optimization flow LOGIC EQUATIONS TECHNOLOGY-INDEPENDENT OPTIMIZATION Factoring Commonality Extraction TECH-DEPENDENT OPTIMIZATION (TECH. MAPPING, TIMING) OPTIMIZED LOGIC NETWORK LIBRARY

Logic optimization flow LOGIC EQUATIONS TECHNOLOGY-INDEPENDENT OPTIMIZATION Factoring Commonality Extraction TECH-DEPENDENT OPTIMIZATION (TECH. MAPPING, TIMING) OPTIMIZED LOGIC NETWORK LIBRARY

Why logic optimization? • Transistor count redution • Circuit count redution • Gate count (fanout) reduction AREA POWER DELAY (Speed) • Area reduction, power reduction and delay reduction improves design

Boolean Optimizations • Involves: Finding common subexpressions. Substituting one expression into another. Factoring single functions. • ì f 1 = AB + AC + AD + AE + A BC D E F=í î f 2 = AB + AC + AD + AF + A BC D F • Find common expressions ì f 1 = A( B + C + D + E) + ABC DE F=í î f 2 = A( B + C + D + F) + ABC DF • Extract and substitute common expression ì g 1 = B + C + D G = í f 1 = A ( g 1 + E ) + A E g 1 ï î f 2 = A ( g 1 + F ) + A F g 1

Algebraic Optimizations • Algebraic techniques view equations as polynomials • Rules of polynomial algebra are used • For e. g. in algebraic substitution (or division) if a function f = f(a, b, c) is divided by g = g(a, b), a and b will not appear in f / g • Boolean algebra rules are not applied

Logic optimization flow LOGIC EQUATIONS TECHNOLOGY-INDEPENDENT OPTIMIZATION Factoring Commonality Extraction TECH-DEPENDENT OPTIMIZATION (TECH MAPPING, TIMING) OPTIMIZED LOGIC NETWORK LIBRARY

Standard cell library • For each cell (e. g. , NANDs, NORs, Invs, AOIs) – Functional information – Timing information • Input slew • Intrinsic delay • Output capacitance – Physical footprint – Power characteristics

Sample Library INVERTER 2 NAND 2 3 NAND 3 4 NAND 4 5

Sample Library - 2 AOI 21 4 AOI 22 5

Mapping via DAG* Covering • Represent network in canonical form Þ subject DAG • Represent each library gate with canonical forms for the logic function Þ primitive DAGs • Each primitive DAG has a cost • Goal: Find a minimum cost covering of the subject DAG by the primitive DAGs * Directed Acyclic Graph

Trivial Covering Reduce netlist into ND 2 gates → subject DAG 7 5 NAND 2 = 21 INV = 10 31 (area cost)

Covering #1 2 INV 2 NAND 2 1 NAND 3 1 NAND 4 =4 =6 =4 =5 19 (area cost)

Covering #2 1 INV 1 NAND 2 2 NAND 3 1 AOI 21 = = 2 3 8 4 17 (area cost)

Multiple fan-out

Partitioning a Graph • Partition input netlist into a forest of trees • Solve each tree optimally • Stitch trees back together

Optimum Tree Covering INV 11 + 2 = 13 AOI 21 4+3=7 NAND 2 2 + 6 + 3 = 11 NAND 2 3+3=6 INV 2 NAND 2 3

DAG Covering steps • Partition DAG into a forest of trees • Normalize the netlist • Optimally cover each tree – Generate all candidate matches – Find optimal match using dynamic programming

For more details on logic opt. … • Refer to Srinivas Devadas’ slides for 6. 373 http: //csg. csail. mit. edu/u/d/devadas/public_html/6. 373/lectures/