ECE 545Digital System Design with VHDL Lecture 2

ECE 545—Digital System Design with VHDL Lecture 2 Digital Logic Refresher Part B – Sequential Logic Building Blocks 1

Lecture Roadmap – Sequential Logic • Sequential Logic Building Blocks • • Flip-Flops, Latches Registers, Shift Registers Counters RAM 2

Textbook References • Sequential Logic Review • Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2 nd or 3 rd Edition • Chapter 7 Flip-flops, Registers, Counters, and a Simple Processors (7. 3 -7. 4, 7. 8 -7. 11 only) • OR your undergraduate digital logic textbook (chapters on sequential logic) 3

Sequential Logic Building Blocks some slides modified from: Brown and Vranesic, “Fundamentals of Digital Logic with VHDL Design, 2 nd Edition” S. Dandamudi, “Fundamentals of Computer Organization and Design” 4

Introduction to Sequential Logic • Output depends on the current input and the internal state • Past inputs effects the internal state • Sequential circuits consist typically of • Storage elements (flip-flop, latch, register, RAM, etc. ) • Combinational logic 5

Introduction (cont’d) Main components of a typical synchronous sequential circuit (synchronous = uses a clock to keep circuits in lock step) INPUT OUTPUT COMBINATIONAL LOGIC NEXT STATE PRESENT STATE S(t) STATEHOLDING STORAGE ELEMENTS (i. e. FLIPFLOPS) S(t+1) CLOCK 6

State-Holding Memory Elements • Latch versus Flip Flop • Latches are level-sensitive: whenever clock is high, latch is transparent • Flip-flops are edge-sensitive: data passes through (i. e. data is sampled) only on a rising (or falling) edge of the clock • Latches cheaper to implement than flip-flops • Flip-flops are easier to design with than latches • In this course, primarily use D flip-flops 7

D Latch vs. D Flip-Flop D Q CLK D CLK Q Latch transparent when clock is high D D Q CLK Q “Samples” D on rising edge of clock 8

D latch Truth table Graphical symbol Clock 0 1 1 Q D Clock D – 0 1 Q(t+1) Q(t) 0 1 Timing diagram t 1 t 2 t 3 t 4 Clock D Q Time 9

D flip-flop Truth table Graphical symbol D Q Clock t 1 Clk D 0 1 0 – 1 – Timing diagram t 2 t 3 Q(t+1) 0 1 Q(t) t 4 Clock D Q Time 10

D Flip-Flop with Asynchronous Set and Reset • Bubble on the symbol means “active-low” Set D Q Q Reset • • When Set = 0, set Q to 1 When Set = 1, do nothing When Reset = 0, set Q to 0 When Reset = 1, do nothing • “Set” and “Reset” also known as “Preset” and “Clear” respectively • In this circuit, Set and Reset are asynchronous • Q changes immediately when preset or clear are active, regardless of clock 11

D Flip-Flop with Synchronous Reset D Reset CLK Reset Q (asynchronous Reset) Q (synchronous Reset) • Asynchronous active-low Reset: Q immediately clears to 0 • Synchronous active-low Reset: Q clears to 0 on rising-edge of clock 12

Register D(3) D Q Q(3) CLK D(2) D Q Q(2) CLK D(1) D Q 4 4 D Q Q(1) CLK D(0) D Q Q(0) CLK Clock • In typical nomenclature, a register is a name for a collection of flip-flops used to hold a bus • All flip-flops of a register share the same clock and control signals 13

Shift Register Sin D Q Q 3 D Q Q 2 D Q Q 1 D Q Q 0 Q Clk (a) Circuit Clk Sin SHIFT REGISTER Q t 0 Sin Q 3 1 0 Q 2 0 Q 1 0 Q 0 = Q 0 t 1 0 0 0 t 2 1 0 0 t 3 1 1 0 t 4 1 1 1 0 1 t 5 0 1 1 1 0 t 6 0 0 1 1 1 t 7 0 0 0 1 1 14

4 -bit Shift Registers: symbols a) with Enable Q 4 b) with Enable and Parallel Load 4 Enable D Q 4 Load Sin Clock 15

Shift Register with Enable: internal structure Sin D Q Q(1) Q(2) Q(3) D Q Q(0) D Q Clock Enable 16

Shift Register with Parallel Load: internal structure Load D(3) D(1) D(2) Sin D Q D D(0) D Q Q D Q Clock Enable Q(3) Q(2) Q(1) Q(0) 17

Synchronous Up Counter enable load D 0 D 1 D 2 D 3 carry Q 0 Q 1 Q 2 Q 3 clock • Enable (synchronous): when high enables the counter, when low counter holds its value • Load (synchronous) : when load = 1, load the desired value into the counter • Output carry: indicates when the counter “rolls over” • D 3 downto D 0, Q 3 downto Q 0 is how to interpret MSB to LSB 18

Random Access Memory (RAM) • More efficient than registers for storing large amounts of data • Can read and write to RAM • Addressable memory • RAM dimensions are: • (number of words) x (bits per word) • Address is m bits, data is n bits • 2 m x n-bit RAM • Example: address is 5 bits, data is 8 bits • 32 x 8 RAM • Write Enable (WE) • When set, writing takes place at the next rising edge n m DIN ADDR DOUT n RAM WE CL K 19

Dual-Port RAM • Two sets of input ports {DINA, ADDRA, WEA} {DINB, ADDRB, WEB} • Two corresponding outputs DOUTA DOUTB • One memory matrix • Possible operations: • Read from two memory locations • Write to two different memory locations • Read from a memory location and write to a memory location (different or the same) n m DINA DOUTA n ADDRA WEA n m DINB RAM DOUTB n ADDRB WEB CL K 20