ECE 491 Senior Design I Lecture 2 Verilog

ECE 491 - Senior Design I Lecture 2 - Verilog Fall 2006 Lab Tomorrow: Meet in 400 AEC 9 AM Bring a Lab Notebook to Lab (choose a partner) HW Due Friday 9/1: Summary of serial communication Handout: “Structural Design with Verilog” Read Sections 1 -5 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette. edu ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 1

Today’s Outline } Overview: Electronic Design with FPGAs } Verilog Part 1 } Language Overview } Combinational Logic • Continuous Assignment • Module Instantiation • always blocks ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 2

FPGA Design Flow HDL (or Schematic) Input } Synthesis } Translate HDL to hardware } Optimize & map to CLBs } Estimate timing Synthesis Placement } Map CLBs to specific locations Routing } Determine how to interconnect CLBs } Program } Download bitstream into FPGA Configured Design ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 3

Hardware Description Languages } Verilog } Designed by one person at Gateway Design Automation (now part of Cadence) } Syntax similar to C } Favored by industrial designers We’ll use Verilog! } IEEE Standard 1364 } VHDL } } Designed by committee for the Department of Defense Syntax similar to Pascal, ADA Favored by government labs, contractors IEEE Standard 1076 ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 4

Verilog Overview } } } } Important Points About Verilog Language Details Basic Module Syntax Combinational Logic Parameters Module Instantiation Sequential Logic Finite State Machines ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 5

Important Points about Verilog } Verilog is designed to model hardware } Hardware is parallel, so execution is parallel } Verilog code is not software! ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 6

Important Points about Verilog (cont’d) } Verilog is based on event-driven simulation } Signal values change at specific time points } Each model: • Activates in response to input events • Creates output events to represent output changes input event A delay=4 A B C output event ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 7

Important Points about Verilog (cont’d) } Verilog was designed as a simulation language } Synthesis added as an afterthought } Only a subset of the language supported for synthesis } Synthesis must match simulated behavior } We’ll focus mostly on the synthesis subset } Structural Descriptions - module instantiations } Behavioral Descriptions • assign - continuous assignments • always blocks } But, we’ll use simulation capabilities for verification } initial blocks } Delay ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 8

Verilog module construct } Key building block of language } declaration - specifies a module interface • Input & output ports connections to outside world • “black box” model - no details about internals } body - specifies contents of "black box" • behavior - what it does • structure - how it's built from other "black boxes" ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 9

Module - A Quick Example } Full Adder : Ports Semicolon module fulladder(a, b, cin, sum, cout); input a, b, cin; Port Declarations output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule NO Semicolon ECE 491 Fall 2006 Continuous Assignment Statements Lecture 2 - Verilog Review 1 10

Comments about the First Example } Verilog describes a circuit as a set of modules } Each module has input and output ports } Single bit } Multiple bit - array syntax } Each port can take on a digital value (0, 1, X, Z) } Three main ways to specify module internals } Continuous assignment statements - assign } Concurrent statements - always } Submodule instantiation (hierarchy) ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 11

Verilog Review - Language Details } Syntax - See Quick Reference Card } Major elements of language: } Lexical Elements (“tokens” and “token separators”) } Data Types and Values } Operators and Precedence ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 12

Verilog Lexical Elements } Whitespace - ignored except as token separators } blank spaces } tabs } newlines } Comments } Single-line comments // } Multi-line comments /* … */ } Operators- unary, binary, ternary } Unary a = ~b; } Binary a = b && c; } Ternary a = (b < c) ? b : c; ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 13

Verilog Numbers } Sized numbers: <size>'<base format><number> } <size> - decimal number specifying number of bits } <base format> - base of number • decimal • hex • binary 'd or 'D 'h or 'H ‘b or ‘B } <number> - consecutive digits • • normal digits 0, 1, …, 9 (if appropriate for base) hex digits x z a, b, c, d, e, f "unknown" digit "high-impedance" digit } Examples 4’b 1111 ECE 491 Fall 2006 12’h 7 af Lecture 2 - Verilog Review 1 16’d 255 14

Verilog Numbers (cont'd) } Unsized numbers } Decimal numbers appearing as constants (236, 5, 15, etc. ) } Bitwidth is simulator-dependent (usually 32 bits) } Negative numbers } sized numbers: '-' before size -8'd 127 -3'b 111 } unsized numbers: '-' before first digit -233 } Underline '_' can be used as a "spacer” 12'b 00010_1010_011 is same as ECE 491 Fall 2006 12'b 000101010011 Lecture 2 - Verilog Review 1 15

Verilog Strings } Anything in quotes is a string: "This is a string" "a / b" } Strings must be on a single line } Treated as a sequence of 1 -byte ASCII values } Special characters - C-like () ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 16

Verilog Identifiers } } Starting character: alphabetic or '_' Following characters: alpha, numeric, or '_' Examples: george _paul "Escaped" identifiers: } } start with backslash follow with any non-whitespace ASCII end with whitespace character Examples: 212 net **xyzzy** $foo } Special notes: } Identifiers are case sensitive } Identifiers may not be reserved words ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 17

Verilog Reserved Words always and assign begin bufif 0 bufif 1 casex casez cmos deassign default defparam disable edge else endcase endfunction endmodule endprimitive endspecify endtable endtask event force forever fork function highz 0 highz 1 if ifnone initial inout input integer join large macromodule medium module nand negedge nmos nor notif 0 notif or output parameter pmos posedge primitive pull 0 pull 1 pulldown pullup rcmos realtime reg release repeat rnmos rpmos rtranif 0 rtranif 1 scalared small specify specparam strong 0 strong 1 supply 0 supply 1 table task time tranif 0 tranif 1 tri 0 tri 1 triand trior trireg vectored wait wand weak 0 weak 1 while wire wor xnor xor ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 18

Verilog Data Types } nets - describe “wire” connections } general purpose: wire } special purpose: supply 0, supply 1, tri 0, tri 1, triand, trior, trireg, wand, wor } registers - variables (assigned values by procedural statement) } } } reg - basic binary values integer - binary word (≥ 32 bits - machine dependent) real - floating point (not supported by synthesis) time - simulation time (not supported in synthesis) realtime - simulation time (not supported in synthesis) ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 19

More about Data Types } Vectors - Multiple-Bit Signals (net or register) wire [31: 0] sum; reg [7: 0] avg; } Arrays - used for memories reg [7: 0] memory [0: 255]; word size ECE 491 Fall 2006 memory size Lecture 2 - Verilog Review 1 20

Verilog Logic Values } Each wire or register type can take on 4 values: } } 0 - Standard binary “FALSE” 1 - Standard binary “TRUE” X - UNKNOWN Z - High Impedance } During simulation, all variables originally X } Complication: x & z sometimes used as “wildcards” (e. g. casex, casez) ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 21

Operators and Precedence } Override with parentheses () when needed ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 22

Verilog Module Declaration } Describes the external interface of a single module } Name } Ports - inputs and outputs } General Syntax: modulename ( port 1, port 2, . . . ); port 1 direction declaration; port 2 direction declaration; reg declarations; wire declarations; module body - “parallel” statements endmodule // note no semicolon (; ) here! ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 23

Verilog Body Declaration “Parallel” Statements } Parallel statements describe concurrent behavior (i. e. , statements which “execute” in parallel) } Types of Parallel Statements: } assign - used to specify simple combinational logic } always - used to specify repeating behavior for combinational or sequential logic } initial - used to specify startup behavior (not supported in synthesis - but useful in simulation!) } module instantiation - used for structure } … and other features useful only in simulation ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 24

Full Adder Example - Again } Full Adder : module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule Continuous Assignment Statements ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 25

Bitwise Operators } Basic bitwise operators: identical to C/C++/Java module inv(a, y); input [3: 0] a; output [3: 0] y; 4 -bit Ports assign y = ~a; endmodule Unary Operator: NOT ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 26

Reduction Operators } Apply a single logic function to multiple-bit inputs module and 8(a, y); input [7: 0] a; output y; assign y = &a; endmodule Reduction Operator: AND equivalent to: a[7] & a[6] & a[5] & a[4] & a[3] & a[2] & a[0] ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 27

Conditional Operators } Like C/C++/Java Conditional Operator module mux 2(d 0, d 1, s, y); input [3: 0] d 0, d 1; input s; output [3: 0] y; assign y = s ? d 1 : d 0; // output d 1 when s=1, else d 0 endmodule ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 28

More Operators } Equivalent to C/C++/Java Operators } Arithmetic: } Comparison: } Shifting: + - * / & == != < <= > >= << >> } Example: module adder(a, b, y); input [31: 0] a, b; output [31: 0] y; assign y = a + b; endmodule } Warning: small expressions can make big hardware! ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 29

Bit Manipulation: Concatenation } { } is the concatenation operator module adder(a, b, y, cout); input [31: 0] a, b; output [31: 0] y; output cout; assign {cout, y} = a + b; endmodule Concatenation (33 bits) ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 30

Bit Manipulation: Replication } { n {pattern} } replicates a pattern n times module signextend(a, y); input [15: 0] a; output [31: 0] y; assign y = {16{a[15]}, a[15: 0]}; endmodule Copies sign bit 16 times ECE 491 Fall 2006 Lower 16 Bits Lecture 2 - Verilog Review 1 31

Internal Signals } Declared using the wire keyword module fulladder(a, b, cin, s, cout); input a, b, cin; output s, cout; wire prop; assign prop = a ^ b; assign s = prop ^ cin; assign cout = (a & b) | (cin & (a | b)); endmodule Important point: these statements “execute” in parallel ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 32

Combinational always blocks } Motivation } assign statements are fine for simple functions } More complex functions require procedural modeling } Basic syntax: Signal list - change activates block always (sensitivity-list) Procedural statement (=, if/else, etc. ) statement or always (sensitivity-list) begin Compound Statement statement-sequence of statements end ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 33

Combinational Modeling with always } Example: 4 -input mux behavioral model module mux 4(d 0, d 1, d 2, d 3, s, y); input d 0, d 1, d 2, d 3; input [1: 0] s; output y; reg y; always @(d 0 or d 1 or d 2 or d 3 or s) case (s) Blocking assignments 2'd 0 : y = d 0; (immediate update) 2'd 1 : y = d 1; 2'd 2 : y = d 2; 2'd 3 : y = d 3; default : y = 1'bx; endcase Endmodule ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 34

Another Example: ALU from ECE 313 module alu(ctl, a, b, result, zero); input [2: 0] ctl; input [31: 0] a, b; output [31: 0] result; output zero; reg [31: 0] result; reg zero; always @(a or b or ctl) begin case (ctl) 3'b 000 : result = a & b; // AND 3'b 001 : result = a | b; // OR 3'b 010 : result = a + b; // ADD 3'b 110 : result = a - b; // SUBTRACT 3'b 111 : if (a < b) result = 32'd 1; else result = 32'd 0; //SLT default : result = 32'hxxxx; endcase if (result == 32'd 0) zero = 1; else zero = 0; endmodule ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 zero ALU 35

Modeling with Hierarchy } Create instances of submodules } Example: Create a 4 -input Mux using mux 2 module } Original mux 2 module: module mux 2(d 0, d 1, s, y); input [3: 0] d 0, d 1; input s; output [3: 0] y; assign y = s ? d 1 : d 0; endmodule ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 36

Modeling with Hierarchy } Create instances of submodules } Example: Create a 4 -input Mux using mux 2 module mux 4(d 0, d 1, d 2, d 3, s, y); input [3: 0] d 0, d 1, d 2, d 3; input [1: 0] s; output [3: 0] y; wire [3: 0] low, high; mux 2 lowmux(d 0, d 1, s[0], low); mux 2 highmux(d 2, d 3, s[0], high); mux 2 finalmux(low, high, s[1], y); endmodule Instance Names ECE 491 Fall 2006 Connections Lecture 2 - Verilog Review 1 37

Data Types and Module Ports } Input ports must always be a wire (net) } Output ports can be wire or reg a b c ECE 491 Fall 2006 wire always @(a or b) x = a ^ b; wire reg wire assign y = ~a; wire xor(z, b, c) (instantiation) wire Lecture 2 - Verilog Review 1 x y z 38

Parameterized Modules } Parameters - define values that can change } Declaration: module mod 1(in 1, in 2, out 1, out 2); parameter N=default-value; input [N-1 : 0] in 1, in 2; output [N-1 : 0] out 1; … Uses Parameter N endmodule Defines Parameter N } Instantiation: Sizes must match wire [7: 0] w, x, y; instantiated value! wire z; mod 1 #(8) my_mod 1(w, x, y, z); Sets Parameter N for instance my_mod 1 ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 39

Parameterized Modules: Example } N-bit 2 -1 multiplexer (parameterized bitwidth) module mux 2( sel, a, b, y ); parameter bitwidth=32; input sel; input [bitwidth-1: 0] a, b; output [bitwidth-1: 0] y; assign y = sel ? b : a; endmodule Defines Parameter bitwidth (default value: 32) Uses Parameter bitwidth to set input, output size } Instantiations mux 2 #(16) my 16 bit_mux(s, a , b, c); mux 2 #(5) my 5 bit_mux(s, d, e, f); mux 2 #(32) my 32 bit_mux(s, g, h, i); mux 2 my. Default 32 bit_mux(s, j, k, l); ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 16 -bit mux 5 -bit mux 32 -bit mux (default) 40

Symbolic Constants with Parameters } Idea: use parameter to name “special constants” parameter RED_ALERT = 2’b 11; parameter YELLOW_ALERT = 2’b 01; parameter GREEN_ALERT = 2’b 00; } Don’t change in module instances } Do this to make your code more understandable } For others reading your code } For yourself reading your code after some time has passed ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 41

Symbolic Constant Example } 7 -segment decoder from Verilog Handout (Part 1) module seven_seg_display_decoder(data, segments); input [3: 0] data; output [6: 0] segments; reg [6: 0] segments; // Segment # abc_defg hex equivalent parameter BLANK = 7’b 111_1111; // h 7 F parameter ZERO = 7’b 000_0001; // h 01 parameter ONE = 7’b 100_1111; // h 4 F parameter TWO = 7’b 001_0010; // h 12 parameter THREE = 7’b 000_0110; // h 06 parameter FOUR = 7’b 100_1100; // h 4 C parameter FIVE = 7’b 010_0100; // h 24 parameter SIX = 7’b 010_0000; // h 20 parameter SEVEN = 7’b 000_1111; // h 0 F parameter EIGHT = 7’b 000_0000; // h 00 parameter NINE = 7’b 000_0100; // h 04 ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 42

Symbolic Constant Example } 7 -segment decoder from Verilog handout (Part 2) always @(data) case (data) 0: segments = ZERO; 1: segments = ONE; 2: segments = TWO; 3: segments = THREE; 4: segments = FOUR; 5: segments = FIVE; 6: segments = SIX; 7: segments = SEVEN; 8: segments = EIGHT; 9: segments = NINE; default: segments = BLANK; endcase endmodule ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 43

Symbolic Constants using `define } Like C/C++, Verilog has a preprocessor } `define - equivalent to #define in C/C++ } Symbolic constant definition: `define ZERO 7’b 0000_0001 } Symbolic constant usage: preface with “`” segments = `ZERO; } Other preprocessor directives } `ifdef } `else } `endif ECE 491 Fall 2006 Used for conditional compilation Lecture 2 - Verilog Review 1 44

More about always } Specifies logic with procedural statements } Simulation model: executes statements in order } Synthesized hardware: matches simulation } “reg” declarations } treat like variables in C or Java } assignment: holds value until a new assignment is made module my_logic(a, b, c, d); input a, b; output c, d; reg c, d; always @(a or b) begin c = a & b; d = b ^ c; endmodule ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 45

Synthesizing Comb. Logic } When no if, case, or loop statements: } Assignment statements generate logic } Outputs are values of last assignments } Logic optimized, reduced during synthesis module my_logic(a, b, c, d); input a, b; output c, d; reg c, d; always @(a or b) begin c = a & b; d = b ^ c; c = d | a; endmodule ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 46

Synthesizing Comb. Logic - if/else } if/else statements become multiplexers } multiplexers follow statement order always @(c or d or x or y) begin if (c == 1’b 1) z = x + y; else z = x - y; if (d == 1’b 0) w = z; else w = x; end ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 47

Synthesizing Comb. Logic if /else if / else } Each else implies mutual exclusion } if / else creates a priority encoder always @(c or d or x or y) begin if (c == 1’b 1) z = x + y; else if (d == 0’b 0) z = x - y; else z = x; end } Use sequential if statements without else if to avoid priority if desired ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 48

Synthesizing Comb. Logic if without else } if without else: output depends on previous value always @(a or x or y) begin w = x + y; if (a == 1’b 1) w = x; end } What if no previous value is specified? } Must preserve the semantics of the language } This requires a latch inference always @(a or x) begin if (a == 1’b 1) w = x; end ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 49

Synthesizing Comb. Logic if without else (latch inference) } if without else: output depends on previous value always @(a or x) begin if (a == 1’b 1) w = x; end } What if no previous value is specified? } Must preserve the semantics of the language } This requires a latch inference to store “old” value } Latch inferences are bad! ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 50

Synthesizing Comb. Logic case statements } Verilog case: treated as if / else. . . always @(e or x or y) begin case (e) 2’b 00 : w = x + y; 2’b 01 : w = x - y; 2’b 10 : w = x & y; default: w = 4’b 0000; endcase end } Use default to avoid latch inference! ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 51

Synthesizing Comb. Logic One Last Pitfall } always must include all inputs in sensitivity list } OR… mismatch between synthesis & simulation! always @(e or x) begin case (e) Missing: or y 2’b 00 : w = x + y; 2’b 01 : w = x - y; 2’b 10 : w = x & y; default: w = 4’b 0000; endcase end ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 52

Synthesizing Comb. Logic One Last Pitfall } Verilog 2001 Alternative (not supported by all tools) always @* begin case (e) 2’b 00 : w = x + y; 2’b 01 : w = x - y; 2’b 10 : w = x & y; default: w = 4’b 0000; endcase end ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 53

About Lab 1 } Goals of Lab 1 } Review Combinational Logic Design with Verilog } Learn about FPGA Design with Verilog } Learn about the Spartan-3 Starter Kit Board (S 3 Board) ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 54

Starter Kit Board - Overview ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 55

S 3 Board: Seven-Segment Display } Segment signals - active low } Digit enables used to “time multiplex” digits ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 56

Using the S 3 Board with Verilog } Top-level module file: s 3 board. v } Contains declarations for all input & output pins • • Switches & pushbuttons LEDs and 7 -segment displays RS-232 port(s) Not used (currently): PS/2 port, VGA port } Use as a starting point for your design } Constraint file: s 3 board. ucf } Contains pin assignments for all inputs & outputs } Uncomment pins that you’re going to use (remove “#”) } These files can be downloaded from the website ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 57

What to Do in Lab 1 } Download “s 3 board. v” and “s 3 board. ucf” } Run ISE and create a new project } } } Add “s 3 board. v” and “s 3 board. ucf” Add Verilog code for a 4 -bit adder Add Verilog code for a 7 -segment decoder with hex digits Connect slide switches to adder inputs Connect 7 -segment decoder to adder output Connect 7 -segment decoder to display LSB } Compile, download, & debug ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 58

Lab 1 - Block Diagram ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 59

Coming Up } Sequential Logic Design with Verilog & FPGAs ECE 491 Fall 2006 Lecture 2 - Verilog Review 1 60