ECE 491 Senior Design I Lecture 11 Timing

ECE 491 - Senior Design I Lecture 11 - Timing and Metastability Fall 2006 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette. edu ECE 491 Fall 2006 Lecture 11 - Timing 1

Where we are } Last Time: } Verilog Coding - Quick Recap } The Datapath/Controller Abstraction } Today: } Timing } Synchronizers & Metastability ECE 491 Fall 2006 Lecture 11 - Timing 2

Review - Flip-Flop Timing Characteristics } Propagation Delay t. CQ } Setup time tsetup } Hold time th DQ clk CLK tsetup th D Q ECE 491 Fall 2006 t. CQ Lecture 11 - Timing 3

Review - Clocks in Sequential Circuits } Controls sequential circuit operation } Register outputs change at beginning of cycle } Combinational logic determines “next state” } Storage elements store new state Register Output Combinational Logic Register Input Adder Mux Clock ECE 491 Fall 2006 Lecture 11 - Timing 4

What Limits Clock Frequency? } Propagation delay - tprop • Logic (including register outputs) • Interconnect } Register setup time - tsetup Register Output Combinational Logic Register Input Adder tclock > tprop+ tsetup Mux tclock = tprop+ tsetup + tslack Clock tprop ECE 491 Fall 2006 tsetup Lecture 11 - Timing 5

Timing in FPGA Design - Constraints } The constraints file specifies timing using the TIMESPEC directive #TIMESPEC <name> = FROM : <source> : TO : <dest> : <time>; } In the “s 3 board. v” file - using predefined groups # Time specifications # #TIMESPEC TS 01 = FROM #TIMESPEC TS 02 = FROM #TIMESPEC TS 03 = FROM #TIMESPEC TS 04 = FROM #TIMESPEC TS 05 = FROM #TIMESPEC TS 06 = FROM #TIMESPEC TS 07 = FROM #TIMESPEC TS 08 = FROM ECE 491 Fall 2006 for 50 MHz clock : : : : FFS : TO : FFS : 20 ns; RAMS : TO : FFS : 20 ns; FFS : TO : RAMS : 20 ns; RAMS : TO : RAMS : 20 ns; FFS : TO : PADS : 20 ns; PADS : TO : FFS : 20 ns; PADS : TO : RAMS : 20 ns; RAMS : TO : PADS : 20 ns; Lecture 11 - Timing 6

Synchronizers } Key idea: make sure inputs don’t change at a “bad time” in sequential circuits 00 in 1’ in 1 10 01 in 2 11 in 3 clk in 1 NS 11 10 01 transient ECE 491 Fall 2006 Lecture 11 - Timing 7

Adding Synchronizers } Add a D Flip-Flop on each asynchronous input } Synchronize each input only once } Q: What happens when set up & hold time violated? in 1_a D Q in 1_s in 2_a D Q in 2_s clk ECE 491 Fall 2006 Lecture 11 - Timing 8

Metastability: When bad things happen to good synchronizers Q: What happens when tsu / th constraints violated? A: It depends, but there are three scenarios 1. Circuit correctly records new D value 1. Circuit retains old D value for an extra cycle 3. Metastability - “stuck” between legal 0 and 1 until it “resolves” CLK tsu th D tclk-q Q 1 Q 2 tclk-q Q 3 Resolution Time tr ECE 491 Fall 2006 Lecture 11 - Timing 9

What Metastability Looks Like Image Source: www. fpga-faq. com ECE 491 Fall 2006 Lecture 11 - Timing 10

Metastability } Two stable states } Vo 1=L, Vo 2=H } Vo 1=H, Vo 2=L } One metastable state } Vo 1 = Vo 2 } Ugly characteristic: unbounded recovery time tr Graphic source: J. Rabaey, Digital Integrated Circuits, © Prentice-Hall, 1996 ECE 491 Fall 2006 Metastable point Lecture 11 - Timing 11

Metastability - “Ball on the Hill” Analogy } Sides of hill = stable states } Top of hill = metastable state } Any small “push” (e. g. , noise) will move the ball off the hill and into a stable state ECE 491 Fall 2006 Lecture 11 - Timing 12

Metastability - Bad News / Good News } Bad news } Metastability is unavoidable } Recovery time is theoretically unbounded } Good news } Can empirically measure recovery times } Can use statistics from recovery times to make failure probability arbitrarily small } Most FPGAs are highly resistant to metastability ECE 491 Fall 2006 Lecture 11 - Timing 13

Measuring Metastability Characteristics } Intentionally cause metastability many times } Measure recovery for each occurrence } Fit recovery times to exponential function Number Of Occurrences tclk-q ECE 491 Fall 2006 Recovery Time Lecture 11 - Timing 14

Designing with Metastability } A synchronizer design at a given clock period provides a fixed amount of resolution time tr } Definition: a synchronization failure occurs when actual recovery time tr-actual > tr } For a given flip-flop, the mean time between failure (MTBF) is given by the formula fclk - System clock freq. a - asynchronous input rate of change. t - empirically derived constant To - empirically derived constant tr - time available for resolution ECE 491 Fall 2006 Lecture 11 - Timing 15

Determining Resolution Time tr } Must leave time for system to respond properly after resolution tr = tclk - tsetup - tprop tsu DQ DQ Comb. Logic clk ECE 491 Fall 2006 Lecture 11 - Timing 16

Resolution Time Example } Suppose that = 100 MHz (tclk = 10 ns) } a = 1 MHz } tprop = 6. 7 ns } tsetup = 1 ns } fclk } Calculate tr: } tr = tclk - tsetup - tprop } tr = 10 ns - 6. 7 ns -1 ns = 2. 3 ns ECE 491 Fall 2006 DQ tprop=6. 7 ns tsu=1 ns DQ Comb. Logic clk Lecture 11 - Timing 17

MTBF Calculation Example } “Typical” values for a 0. 25µm ASIC library flip-flop } t = 0. 31 ns } To = 9. 6 as } tr = 2. 3 ns “a” = 10 -18 } MTBF = 20. 1 days - unacceptable! ECE 491 Fall 2006 Lecture 11 - Timing 18

What happens if we halve fclk? } Suppose that } } fclk = 50 MHz (tclk = 20 ns) a = 1 MHz tprop = 6. 7 ns tsetup = 1 ns } Calculate tr and MTBF: } tr = tclk - tsetup - tprop } tr = 20 ns - 6. 7 ns -1 ns = 12. 3 ns } MTBF = 5. 7 X 1028 seconds = 1. 8 X 1021 years ECE 491 Fall 2006 Lecture 11 - Timing 19

Reality Check: What about FPGAs? } Metastability info in FPGAs is scarce } One refrerence: Peter Alfke, “Metastability Delay and Mean Time Between Failures in Virtex-II Pro FFs”, October 2002. } Some statistical measurements for Virtex-II Pro FPGAs } Major conclusion: Metastability issues are not much of a problem ECE 491 Fall 2006 Lecture 11 - Timing 20

MTBF Calculation Example - Virtex II Pro } Values from a Xilinx Technical note: } t = 0. 02 ns - 0. 05 ps (assume 0. 05 ps) } To = not given, but assume = 9. 6 as “a” = 10 -18 } tr = 2. 3 ns } MTBF = 9. 89 X 1022 seconds = 7, 53 X 1016 years - not to worry! ECE 491 Fall 2006 Lecture 11 - Timing 21

Alternative: Dual-Stage Synchronizer } Increased value for tr: tr = tclk - tsu - tpr tr = 10 ns - 1 ns = 9 ns DQ tprop tsu DQ DQ Comb. Logic clk ECE 491 Fall 2006 Lecture 11 - Timing 22

Dual-Stage MTBF Calculation } “Typical” values for a 0. 25µm ASIC library flip-flop } t = 0. 31 ns } To = 9. 6 as } tr = 9 ns “a” = 10 -18 } MTBF = ? ECE 491 Fall 2006 Lecture 11 - Timing 23

Other Synchronizer Alternatives } Metastability-hardened SYNC flip-flops } Multiple-Stage Synchronizers } Reduced-Clock Synchronizers ECE 491 Fall 2006 Lecture 11 - Timing 24

What to Do About Metastability } } } Start with simple synchronizer (single flip-flop) Calculate MTBF for your system Decide if it's acceptable If not, use a different design OR different design: } Two-stage flip-flop } Reduced-clock synchronizers ECE 491 Fall 2006 Lecture 11 - Timing 25

Coming Up } } System Design ASM Diagrams Manchester Coding Ethernet ECE 491 Fall 2006 Lecture 11 - Timing 26