ECE 448 Lecture 5 FPGA Devices ECE 448

  • Slides: 49
Download presentation
ECE 448 Lecture 5 FPGA Devices ECE 448 – FPGA and ASIC Design with

ECE 448 Lecture 5 FPGA Devices ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Required reading • P. Chu, FPGA Prototyping by VHDL Examples Chapter 2, Overview of

Required reading • P. Chu, FPGA Prototyping by VHDL Examples Chapter 2, Overview of FPGA and EDA Software • 7 Series FPGAs Configurable Logic Block: User Guide § Overview § Functional Details • P. Chu, FPGA Prototyping by VHDL Examples Appendices A 1 -A 3 2

What is an FPGA? Configurable Logic Blocks Block RAMs I/O Blocks Block RAMs ECE

What is an FPGA? Configurable Logic Blocks Block RAMs I/O Blocks Block RAMs ECE 448 – FPGA and ASIC Design with VHDL 3

Modern FPGA RAM blocks Multipliers/DSP units Logic resources (#Logic resources, #Multipliers/DSP units, #RAM_blocks) Graphics

Modern FPGA RAM blocks Multipliers/DSP units Logic resources (#Logic resources, #Multipliers/DSP units, #RAM_blocks) Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www. mentor. com) 4

Major FPGA Vendors SRAM-based FPGAs ~ 50% of the market • Xilinx, Inc. ~

Major FPGA Vendors SRAM-based FPGAs ~ 50% of the market • Xilinx, Inc. ~ 85% • Intel ~ 37% of the market (until 2015, Altera Corp. ) • Lattice Semiconductor • Atmel (since 2016, subsidiary of Microchip Technology) • Achronix Semiconductor • Tabula (went out of business in 2015) Flash & antifuse FPGAs • Microsemi So. C Products Group (until 2010 Actel) • Quick Logic Corp. ECE 448 – FPGA and ASIC Design with VHDL 5

Xilinx u Primary products: FPGAs and the associated CAD software Programmable Logic Devices u

Xilinx u Primary products: FPGAs and the associated CAD software Programmable Logic Devices u u CAD Software Main headquarters in San Jose, CA Fabless* Semiconductor and Software Company u u TSMC (Taiwan) UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} Seiko Epson (Japan) Samsung (Korea) ECE 448 – FPGA and ASIC Design with VHDL 6

Xilinx FPGA Families Technology Low-cost Mid-range 220 nm 180 nm Virtex Spartan-II, Spartan-IIE 120/150

Xilinx FPGA Families Technology Low-cost Mid-range 220 nm 180 nm Virtex Spartan-II, Spartan-IIE 120/150 nm 90 nm 65 nm 40 nm 28 nm High-performance Virtex-II, Virtex-II Pro Spartan-3 Virtex-4 Virtex-5 Spartan-6 Kintex-7 Virtex-6 Virtex-7 20 nm Kintex Ultra. SCALE Virtex Ultra. SCALE 16 nm Kintex Ultra. SCALE+ Virtex Ultra. SCALE+ Artix-7

FPGA Family 8

FPGA Family 8

Artix-7 FPGA Family GMT – Clock Management Tile, combining Phase-Locked Loop (PLL) and Mixed-Mode

Artix-7 FPGA Family GMT – Clock Management Tile, combining Phase-Locked Loop (PLL) and Mixed-Mode Clock Manager (MMCM) PCIe – PCI Express Unit GTP – Gigabit Transceiver XADC – Xilinx Analog Mixed Signal Module ECE 448 – FPGA and ASIC Design with VHDL 9

CLB Structure ECE 448 – FPGA and ASIC Design with VHDL George Mason University

CLB Structure ECE 448 – FPGA and ASIC Design with VHDL George Mason University

General structure of an FPGA The Design Warrior’s Guide to FPGAs Devices, Tools, and

General structure of an FPGA The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www. mentor. com) ECE 448 – FPGA and ASIC Design with VHDL 11

Xilinx Artix-7 CLB ECE 448 – FPGA and ASIC Design with VHDL 12

Xilinx Artix-7 CLB ECE 448 – FPGA and ASIC Design with VHDL 12

Row & Column Relationship Between CLBs & Slices ECE 448 – FPGA and ASIC

Row & Column Relationship Between CLBs & Slices ECE 448 – FPGA and ASIC Design with VHDL 13

Basic Components of the Slice LUTs Storage Elements 14

Basic Components of the Slice LUTs Storage Elements 14

Example of a 4 -input LUT (Look-Up Table) (used in earlier families of FPGAs)

Example of a 4 -input LUT (Look-Up Table) (used in earlier families of FPGAs) • Look-Up tables are primary elements for logic implementation • Each LUT can implement any function of 4 inputs ECE 448 – FPGA and ASIC Design with VHDL 15

LUT of Artix-7 ECE 448 – FPGA and ASIC Design with VHDL 16

LUT of Artix-7 ECE 448 – FPGA and ASIC Design with VHDL 16

17

17

Reset and Set Configurations • • • No set or reset Synchronous reset Asynchronous

Reset and Set Configurations • • • No set or reset Synchronous reset Asynchronous set (preset) Asynchronous reset (clear) ECE 448 – FPGA and ASIC Design with VHDL 18

Two Different Types of Slices in Artix-7 ECE 448 – FPGA and ASIC Design

Two Different Types of Slices in Artix-7 ECE 448 – FPGA and ASIC Design with VHDL 19

SLICEL 20

SLICEL 20

u Each Slice. L and Slice. M contains separate logic and routing for the

u Each Slice. L and Slice. M contains separate logic and routing for the fast generation MSB of sum & carry signals • Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters u Carry logic is independent of normal logic and routing resources LSB Carry Logic Routing Fast Carry Logic 21

Accessing Carry Logic u All major synthesis tools can infer carry logic for arithmetic

Accessing Carry Logic u All major synthesis tools can infer carry logic for arithmetic functions • • Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then…) Counters (count <= count +1) 22

23

23

SLICEM 24

SLICEM 24

Xilinx Multipurpose LUT (MLUT) 32 -bit SR 64 x 1 RAM 64 x 1

Xilinx Multipurpose LUT (MLUT) 32 -bit SR 64 x 1 RAM 64 x 1 ROM (logic) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www. mentor. com) 25

Single-port 64 x 1 -bit RAM 26

Single-port 64 x 1 -bit RAM 26

Single-port 64 x 1 -bit RAM 27

Single-port 64 x 1 -bit RAM 27

Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: • Single-port 128 x

Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: • Single-port 128 x 1 -bit RAM: • Dual-port 64 x 1 -bit RAM : RAM 128 x 1 S RAM 64 x 1 D Memories built of 4 MLUTs: • • Single-port 256 x 1 -bit RAM: RAM 256 x 1 S Dual-port 128 x 1 -bit RAM: RAM 128 x 1 D Quad-port 64 x 1 -bit RAM: RAM 64 x 1 Q Simple-dual-port 64 x 3 -bit RAM: RAM 64 x 3 SDP (one address for read, one address for write) 28

Dual-port 64 x 1 RAM • • Dual-port 64 x 1 -bit RAM :

Dual-port 64 x 1 RAM • • Dual-port 64 x 1 -bit RAM : Single-port 128 x 1 -bit RAM: 64 x 1 D 128 x 1 S 29

Dual-port 64 x 1 RAM • • Dual-port 64 x 1 -bit RAM :

Dual-port 64 x 1 RAM • • Dual-port 64 x 1 -bit RAM : Single-port 128 x 1 -bit RAM: ECE 448 – FPGA and ASIC Design with VHDL 64 x 1 D 128 x 1 S 30

Total Size of Distributed RAM in Artix-7 31

Total Size of Distributed RAM in Artix-7 31

MLUT as a 32 -bit Shift Register (SRL 32) ECE 448 – FPGA and

MLUT as a 32 -bit Shift Register (SRL 32) ECE 448 – FPGA and ASIC Design with VHDL 32

Input/Output Blocks (IOBs) ECE 448 – FPGA and ASIC Design with VHDL George Mason

Input/Output Blocks (IOBs) ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Basic I/O Block Structure D Q EC Three-State FF Enable Clock SR Three-State Control

Basic I/O Block Structure D Q EC Three-State FF Enable Clock SR Three-State Control Set/Reset D Q EC Output FF Enable SR Output Path Direct Input FF Enable Registered Input Q D EC Input Path SR ECE 448 – FPGA and ASIC Design with VHDL 34

IOB Functionality • IOB provides interface between the package pins and CLBs • Each

IOB Functionality • IOB provides interface between the package pins and CLBs • Each IOB can work as uni- or bi-directional I/O • Outputs can be forced into High Impedance • Inputs and outputs can be registered • advised for high-performance I/O • Inputs can be delayed ECE 448 – FPGA and ASIC Design with VHDL 35

Family Attributes ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Family Attributes ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Artix-7 FPGA Family ECE 448 – FPGA and ASIC Design with VHDL 37

Artix-7 FPGA Family ECE 448 – FPGA and ASIC Design with VHDL 37

FPGA device present on the Digilent Nexys 4 DDR board XC 7 A 35

FPGA device present on the Digilent Nexys 4 DDR board XC 7 A 35 T- 1 CPG 236 C Artix-7 family Size Speed Grade 236 pins Package type Commercial temperature range 0°C – 85° C ECE 448 – FPGA and ASIC Design with VHDL 38

FPGA Design Process 39

FPGA Design Process 39

FPGA Design process (1) Design and implement a simple unit permitting to speed up

FPGA Design process (1) Design and implement a simple unit permitting to speed up encryption with RC 5 -similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…. . Specification / Pseudocode On-paper hardware design (Block diagram & ASM chart) VHDL description (Your Source Files) Library IEEE; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; Functional simulation entity RC 5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Synthesis Post-synthesis simulation

FPGA Design process (2) Implementation Timing simulation Results Configuration On chip testing

FPGA Design process (2) Implementation Timing simulation Results Configuration On chip testing

Synthesis George Mason University

Synthesis George Mason University

Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A 1:

Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A 1: STD_LOGIC; signal B 1: STD_LOGIC; signal Y 1: STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A 1<=A when (NEG_A='0') else not A; B 1<=B when (NEG_B='0') else not B; Y<=Y 1 when (NEG_Y='0') else not Y 1; MUX_0<=A 1 and B 1; MUX_1<=A 1 or B 1; MUX_2<=A 1 xor B 1; MUX_3<=A 1 xnor B 1; with (L 1 & L 0) select Y 1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; 43

Circuit netlist (RTL view) 44

Circuit netlist (RTL view) 44

Implementation George Mason University

Implementation George Mason University

Mapping LUT 0 FF 1 LUT 1 FF 2 LUT 2 46

Mapping LUT 0 FF 1 LUT 1 FF 2 LUT 2 46

Placing FPGA CLB SLICES 47

Placing FPGA CLB SLICES 47

Routing FPGA Programmable Connections 48

Routing FPGA Programmable Connections 48

Two main stages of the FPGA Design Flow Implementation Synthesis Technology dependent Technology independent

Two main stages of the FPGA Design Flow Implementation Synthesis Technology dependent Technology independent RTL Synthesis - Code analysis - Derivation of main logic constructions - Technology independent optimization - Creation of “RTL View” Map Place & Route - Mapping of extracted logic structures to device primitives - Technology dependent optimization - Application of “synthesis constraints” -Netlist generation - Creation of “Technology View” Configure - Placement of generated netlist onto the device -Choosing best interconnect structure for the placed design -Application of “physical constraints” - Bitstream generation - Burning device