ECE 448 Lecture 16 FixedPoint Representation of Real

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ECE 448 Lecture 16 Fixed-Point Representation of Real Numbers in VHDL 2008 ECE 448

ECE 448 Lecture 16 Fixed-Point Representation of Real Numbers in VHDL 2008 ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Acknowledgments This set of slides is partially based on course materials developed by Dr.

Acknowledgments This set of slides is partially based on course materials developed by Dr. David Hwang - Harvard University (formerly GMU) Mr. Amos Zaslavsky - Technion – Israel Institute of Technology ECE 448 – FPGA and ASIC Design with VHDL 2

Motivation Topic of Lab 5 ECE 448 – FPGA and ASIC Design with VHDL

Motivation Topic of Lab 5 ECE 448 – FPGA and ASIC Design with VHDL 3

Julia Set Fractal for c=-1+0∙i 4

Julia Set Fractal for c=-1+0∙i 4

Julia Set Fractal for c=− 0. 5+0. 5∙i 5

Julia Set Fractal for c=− 0. 5+0. 5∙i 5

The Julia Set Fractal • Checking whether a given pixel belongs to a fractal

The Julia Set Fractal • Checking whether a given pixel belongs to a fractal involves a sequence of calculations given by the equation: zn+1 = zn 2 + zn + c zn+1, zn, and c are complex numbers! 6

Refresher on Complex Numbers a = ax + ay∙i Real Part ax=Re(a) Square root

Refresher on Complex Numbers a = ax + ay∙i Real Part ax=Re(a) Square root of -1 Imaginary Part ay=Im(a) i 2 = − 1 Examples of operations on complex numbers: (2. 5 + 5. 0∙i ) + (4. 0 + 0. 8∙i) = 6. 5 + 5. 8∙i (2. 5 + 5. 0∙i ) − (4. 0 + 0. 8∙i) = − 1. 5 + 4. 2∙i (2. 5 + 5. 0∙i ) ∙ (4. 0 + 0. 8∙i) = 2. 5∙ 4. 0+2. 5∙ 0. 8∙i+ 5. 0∙ 4. 0∙i+5. 0∙ 0. 8∙i 2= = (10. 0 -4. 0) + (2. 0+20. 0)∙i = 6. 0+22. 0∙i (2. 5 + 5. 0∙i )2 = 2. 52 + 2∙ 2. 5∙ 5. 0∙i + 5. 02∙i 2 = 6. 25 – 25. 0 + 25. 0∙i = = -18. 75 + 25. 0∙i 7

The quadratic recurrence equation z = z 2 + z + c where z

The quadratic recurrence equation z = z 2 + z + c where z = zx + zy∙i c = cx + cy∙i z = z 2 + z + c = (zx + zy∙i)2 + (zx + zy∙i) + (cx + cy∙i) = = (zx 2 – zy 2) + 2∙zx∙zy∙i + (zx + cx) + (zy + cy)∙i = = (zx 2 – zy 2 + zx + cx) + (2∙zx∙zy + cy)∙i 8

Pseudocode In the pseudocode below, z 0=z 0 x+i·z 0 y, corresponds to one

Pseudocode In the pseudocode below, z 0=z 0 x+i·z 0 y, corresponds to one pixel of the display region. -2 ≤ z 0 x=Re(z 0) < 2 -1. 5 < z 0 y=Im(z 0) ≤ 1. 5 0 y=0. . 479 z 0 y=1. 5. . -1. 5+step -1. 5 479 480 -2 0 z 0 x=-2. . 2 x=0. . 640 2 -step 2 639 640 (x, y) (zx 0, zy 0) 9

Pseudocode (with complex numbers) for z 0 y = -1. 5+step to 1. 5,

Pseudocode (with complex numbers) for z 0 y = -1. 5+step to 1. 5, step 3/480 do for z 0 x = -2 to 2 -step, step 4/640 do { iteration = 0 z = z 0 x + z 0 y∙i while( |z| < 2) && (iteration < MAX_ITER) ) { z = z 2 + z + c // the quadratic recurrence equation iteration++ } if |z| < 2 pixel corresponding to z 0 x, z 0 y belongs to a fractal else pixel corresponding to z 0 x, z 0 y does not belong to a fractal } // next zx 0 } // next zy 0 } 10

Pseudocode (with real numbers) for z 0 y = -1. 5+step to 1. 5,

Pseudocode (with real numbers) for z 0 y = -1. 5+step to 1. 5, step 3/480 do for z 0 x = -2 to 2 -step, step 4/640 do { iteration = 0 zx = z 0 x zy = z 0 y while( (zx 2 + zy 2 < 4) && (iteration < MAX_ITER) ) { zxtemp = zx 2 – zy 2 + zx + cx zytemp = 2 · zx · zy + cy zx = zxtemp zy = zytemp iteration++ } 11

Recommended Representation of Real Numbers • You are expected to use the Q 4.

Recommended Representation of Real Numbers • You are expected to use the Q 4. 28 fixed-point representation – 4 integer bits – 28 fractional bits • Addition/Subtraction performed as usual • Multiplication of two Q 4. 28 numbers results in a Q 8. 56 number, which should be converted back to Q 4. 28 12

Fixed-Point Representation ECE 448 – FPGA and ASIC Design with VHDL 13

Fixed-Point Representation ECE 448 – FPGA and ASIC Design with VHDL 13

Fixed-Point Number Representations • Fixed-point number representations can be generally categorized as unsigned or

Fixed-Point Number Representations • Fixed-point number representations can be generally categorized as unsigned or signed • Unsigned numbers represent non-negative numbers; signed numbers represent negative and positive numbers • We focus on: • Unsigned binary • Two's complement (signed) 14

Unsigned Fixed-Point Representation ECE 448 – FPGA and ASIC Design with VHDL 15

Unsigned Fixed-Point Representation ECE 448 – FPGA and ASIC Design with VHDL 15

Unsigned Binary Representation N total bits X = x. K-1 x. K-2 … x

Unsigned Binary Representation N total bits X = x. K-1 x. K-2 … x 1 x 0. x-1 x-2 … x-L K integer bits L fractional bits • K integer bits, L fractional bits • More integer bits, the larger the maximum representable value • Larger the L, the greater the precision • Notation QK. L • K = number of integer bits • L = number of fractional bits 16

Unsigned Binary Examples Q 7. 0 example : 0100101. = 3710 Q 2. 3

Unsigned Binary Examples Q 7. 0 example : 0100101. = 3710 Q 2. 3 example : 01. 001 = 9/8 = 1. 12510 Q 1. 4 example : 0. 1001 = 9/16 = 0. 562510 Q 0. 7 example : . 0001001 = 9/128 = 0. 070312510 17

Maximum Representable Range • QK. L unsigned number has decimal range: • Minimum: 0

Maximum Representable Range • QK. L unsigned number has decimal range: • Minimum: 0 • Maximum: 2 K-2 -L = (2 K+L-1) / 2 L = (2 N-1) / 2 L which is obtained when xi=1 for all i • Exact representable range: 0 ≤ X ≤ 2 K-2 -L • Rule of thumb: range of number X in QK. L notation • 0 ≤ X < 2 K • The number of integer bits K largely determines the maximum representable range 18

Unsigned Binary Maximum Representable Range Examples Q 7. 0 rule of thumb: 0 ≤

Unsigned Binary Maximum Representable Range Examples Q 7. 0 rule of thumb: 0 ≤ X < 128 (K=7) min: 0000000 = (0)10 max: 1111111 = (27 -1) / 20 = 12710 Q 2. 3 rule of thumb: 0 ≤ X < 4 (K=2) min: 00. 000 = (0)10 max: 11. 111 = (25 -1) / 23 = 3. 875 Q 1. 4 rule of thumb: 0 ≤ X < 2 (K=1) min: 0. 0000 = (0)10 max: 1. 1111 = (25 -1) / 24 = 1. 9375 Q 0. 7 rule of thumb: 0 ≤ X < 1 (K=0) min: . 0000000 = (0)10 max: . 1111111 = (27 -1) / 27 = 0. 9921875 19

Signed Fixed-Point Representation ECE 448 – FPGA and ASIC Design with VHDL 20

Signed Fixed-Point Representation ECE 448 – FPGA and ASIC Design with VHDL 20

Two's Complement Notation N total bits X = x. K-1 x. K-2 … x

Two's Complement Notation N total bits X = x. K-1 x. K-2 … x 1 x 0. x-1 x-2 … x-L L fractional bits K integer bits K-2 X = x. K-1 ・ (-2 K-1) + • K integer bits, L fractional bits • More integer bits, the larger the maximum representable value • Larger the L, the greater the precision • Notation QK. L • K = number of integer bits • L = number of fractional bits 21

Two's Complement Examples Q 7. 0 examples: positive: 0100101. = 3710 negative: 1001011. =

Two's Complement Examples Q 7. 0 examples: positive: 0100101. = 3710 negative: 1001011. = -64 + 8 + 2 + 1 = (-53)10 Q 2. 3 examples: positive: 01. 001 = 9/8 = (1. 125)10 negative: 11. 100 = (-16+8+4)/8 = (-0. 5)10 Q 1. 4 examples: positive: 0. 1001 = 9/16 = (0. 5625)10 negative: 1. 1100 = (-16+8+4)/16 = (-0. 25)10 22

Maximum Representable Range • QK. L signed number has decimal range: • Minimum: -2

Maximum Representable Range • QK. L signed number has decimal range: • Minimum: -2 K-1 which is obtained when xi=1 for i=K-1 and xi=0 otherwise • Minimum value is the largest negative value • Maximum: 2 K-1 -2 -L = (2 N-1 -1) / 2 L which is obtained when xi=0 for i=K-1 and xi=1 otherwise • Maximum value is the largest positive value • Exact representable range: -2 K-1 ≤ X ≤ 2 K-1 -2 -L • Range is asymmetric • Rule of thumb: range of number X in QK. L notation • -2 K-1 ≤ X < 2 K-1 • The number of integer bits K largely determines the maximum representable range 23

Two's Complement Maximum Representable Range Examples Q 7. 0 Rule of thumb -64 ≤

Two's Complement Maximum Representable Range Examples Q 7. 0 Rule of thumb -64 ≤ X < 64 (K = 7) minimum: 1000000. = (-64)10 maximum: 0111111. = (63)10 Q 2. 3 Rule of thumb -2 ≤ X < 2 (K= 2) minimum: 10. 000 = (-2. 0)10 maximum: 01. 111 = 15/8 = (1. 875)10 Q 1. 4 Rule of thumb -1 ≤ X < 1 (K= 1) minimum : 1. 0000 = (-1. 0)10 maximum: 0. 1111 = 15/16 = (0. 9375)10 24

Two's Complement in a nutshell • Values starting with '0' are non-negative • Values

Two's Complement in a nutshell • Values starting with '0' are non-negative • Values starting with '1' are negative • To obtain decimal value, invert all bits, add LSB, mod by 2 K • Example Q 4. 0: i. e. 1110 = -(0001 + 0001) mod 24 = 0010 = (-2)10 • Example Q 4. 2: i. e. 11. 00 = -(00. 11 + 00. 01) mod 22= (01. 00) = (-1)10 • The decimal value 0 is not redundant • Can only be represented by all zeros, i. e. 0000 • For a two's complement number QK. L • Exact representable range: -2 K-1 ≤ X ≤ 2 K-1 -2 -L • Range is asymmetric 25

Fixed-Point Representation in VHDL-93 ECE 448 – FPGA and ASIC Design with VHDL 26

Fixed-Point Representation in VHDL-93 ECE 448 – FPGA and ASIC Design with VHDL 26

A Word on Notation in VHDL N total bits X = x. K-1 x.

A Word on Notation in VHDL N total bits X = x. K-1 x. K-2 … x 1 x 0. x-1 x-2 … x-L K integer bits VHDL: x(N-1) L fractional bits VHDL: x(0) • In VHDL-93, we use unsigned(N-1 downto 0) to represent an unsigned QK. L number and signed(N-1 downto 0) to represent a signed QK. L number, where N=K+L • So x(N-1) in VHDL refers to the digit x. K-1 and x(0) in VHDL refers to the digit x-L • The VHDL designer must keep track of the 27

Fixed-Point Representation in VHDL 2008 ECE 448 – FPGA and ASIC Design with VHDL

Fixed-Point Representation in VHDL 2008 ECE 448 – FPGA and ASIC Design with VHDL 28

Subsequent versions of VHDL • IEEE-1076 1987 • IEEE-1076 1993 ← most commonly supported

Subsequent versions of VHDL • IEEE-1076 1987 • IEEE-1076 1993 ← most commonly supported by CAD tools • IEEE-1076 2000 (minor changes) • IEEE-1076 2002 (minor changes) • IEEE-1076 2008 ← supported by the new generation of CAD tools, such as Xilinx Vivado 29

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Example: 45

Example: 45

Basic Fixed Point Operations -- Std libraries library ieee; use ieee. std_logic_1164. all; --

Basic Fixed Point Operations -- Std libraries library ieee; use ieee. std_logic_1164. all; -- Fixed point libraries library ieee_proposed; use ieee_proposed. fixed_pkg. all; Because not all features of VHDL 2008 are supported in the standard ieee library 46

Basic Fixed Point Operations entity Fixed_Test is Port ( A_F B_F OPCODE S_F );

Basic Fixed Point Operations entity Fixed_Test is Port ( A_F B_F OPCODE S_F ); end Fixed_Test; : : in in in out sfixed(3 downto -28); std_logic_vector(1 downto 0); sfixed(3 downto -28) 47

Basic Fixed Point Operations architecture Dataflow of Fixed_Test is signal ADD_F : sfixed(4 downto

Basic Fixed Point Operations architecture Dataflow of Fixed_Test is signal ADD_F : sfixed(4 downto -28); signal SUB_F : sfixed(4 downto -28); signal MUL_F : sfixed(7 downto -56); begin -- Addition : -- Addition between 2 Fixed point number, each Q 4. 28 will -- yield a number that is Q 5. 28 ADD_F <= A_F + B_F; -- Subtraction between 2 Fixed point numbers, each with -- Q 4. 28 gives a Q 5. 28 number SUB_F <= A_F - B_F; 48

Basic Fixed Point Operations -- Multiplication between 2 Fixed point numbers, each with --

Basic Fixed Point Operations -- Multiplication between 2 Fixed point numbers, each with -- Q 4. 28 gives Q 8. 56 number as result MUL_F <= A_F * B_F; -- Truncate the results to show the with OPCODE select S_F <= ADD_F(3 downto -28) SUB_F(3 downto -28) MUL_F(3 downto -28) to_sfixed(0, 3, -28) numbers as Q 4. 28 when "01", "10", "11", others; end Dataflow; 49

Setting the Representation for Display During Simulation 50

Setting the Representation for Display During Simulation 50

Setting the Representation for Display During Simulation 51

Setting the Representation for Display During Simulation 51

Basic Fixed Point Operations Simulation Addition 52

Basic Fixed Point Operations Simulation Addition 52

Basic Fixed Point Operations Simulation Subtraction 53

Basic Fixed Point Operations Simulation Subtraction 53

Basic Fixed Point Operations Simulation Multiplication 54

Basic Fixed Point Operations Simulation Multiplication 54

Important Recommendations! For Vivado 2019. 1, in order to use the types ufixed and

Important Recommendations! For Vivado 2019. 1, in order to use the types ufixed and sfixed: • Include in your project special packages to be provided on the course web page for Lab 5 fixed_float_types_c. vhd fixed_pkg_c. vhd • Set the library to which these packages should be compiled to ieee_proposed • Set the type of all project files to vhdl 2008 • Include at the top of a VHDL file using ufixed or sfixed • library ieee_proposed; • use ieee_proposed. fixed_pkg. all; 55

Single iteration of the Julia fractal set calculations • All the fixed-point inputs and

Single iteration of the Julia fractal set calculations • All the fixed-point inputs and the outputs have to be represented as Q 4. 28 signed fixed-point numbers. • The calculations to implement are as follows zx_o = zx 2 – zy 2 + zx + cx zy_o = 2·zx·zy + cy overflow = 1 if (zx_o 2 + zy_o 2 >= 4) else 0 56

Single iteration of the Julia fractal set calculations The inputs and outputs of the

Single iteration of the Julia fractal set calculations The inputs and outputs of the module can be defined as follows: zx : Signed Fixed-Point input zy : Signed Fixed-Point input zx_o : Signed Fixed-Point output zy_o : Signed Fixed-Point output overflow : std_logic output The Generics of the module can be defined as cx : Signed Fixed-Point cy : Signed Fixed-Point 57