ECE 448 Lecture 15 Overview of Embedded So

ECE 448 Lecture 15 Overview of Embedded So. C Systems ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Required Reading • P. Chu, FPGA Prototyping by VHDL Examples Chapter 8, Overview of Embedded So. C Systems • Source Code of Examples http: //academic. csuohio. edu/chu_p/rtl/fpga_mcs_vhdl. html • Basys 3 FPGA Board Reference Manual 7. VGA Port ECE 448 – FPGA and ASIC Design with VHDL 2

Embedded Systems vs. General-Purpose Computing Source: ETHZ, Prof. Lothar Thiele

Types of Embedded Systems Low-End High-End Example: microwave oven Example: camera Features: simple control functions & user interface Features: 1. input/output, menu, storing image files 2. preprocessing & data compression Implementation: 8 -bit single-chip microcontroller Implementation: 1. Microcontroller 2. Hardware accelerator

FPGA with Soft Processor Core = FPGA-Based System on Chip (So. C) Source: The Zynq Book

Simplified Hardware Architecture of an Embedded So. C I/O Devices Hardware Accelerator Source: The Zynq Book

IP Cores (Intellectual Property Cores) • blocks of logic used in developing FPGA or ASIC systems • essential elements of design reuse • part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. • ideally, an IP core should be entirely portable – that is, able to easily be inserted into any vendor technology or design methodology • can be developed by the device manufacturers, third-party vendors, or the users themselves

Classification of IP Cores • Hard cores - physical manifestations of the IP design; best for plug-and-play applications; less portable and flexible than the other two types of cores • Firm (sometimes called semi-hard ) cores carry placement data but are configurable to various applications • Soft cores exist either as a netlist (a list of the logic gates and associated interconnections) or hardware description language ( HDL ) code

What is Software/Hardware Codesign? Integrated design of systems that consist of hardware and software components • Analysis of HW/SW boundaries and interfaces • Evaluation of design alternatives

Software vs. Hardware Trade-offs Source: A Practical Introduction to Hardware/Software Codesign

Why Codesign?

The Embedded So. C Design Process • Partition the tasks to software routines and hardware accelerators • Design user custom IP cores if needed • Develop the hardware • Develop the software • Implement the hardware and software and perform testing

IP-Centered So. C Development Flow

Elements of the Development Flow • hardware platform specification file: contains the “definition” of the So. C design, including the processor configuration, memory size and structure, I/O peripheral cores used, memory address mapping, etc. • BSP (board support package): a mechanism to encapsulate the system codes; a customized collection of device drivers and initialization routines that support a particular system • device driver: a set of routines that operate or control a particular peripheral device. A driver acts as a “translator” between the hardware peripheral and application programs and enables the application programs to access peripheral functions without needing to know precise details. • . elf file: the Executable and Linkable Format

Custom IP Core Development • Design a custom digital circuit to implement the computation algorithm or special functionality • Derive an interface to connect the circuit to the bus or interconnect structure of the vendor's IP framework. • Develop a device driver to control the new hardware core and integrate it into vendor's software library

FPro System FPGA Prototyping” or “Fun and Professional • Simple. It defines a simple synchronous bus protocol and a straightforward device driver structure. Once a hardware circuit is developed, it can be converted to an IP core by adding a simple interface circuit and a device driver. • Functional. It provides a variety of I/O peripherals and commonly used serial interfaces (UART, SPI, and I 2 C) and includes working device drivers. It resembles a bare-metal 32 bit microprocessor board and can implement real-world projects targeted for this type of boards.

FPro System (cont. ) FPGA Prototyping” or “Fun and Professional • Portable. Except for the processor, FPro So. C's IP cores are developed from scratch in HDL and do not use any vendor's proprietary components. The bus protocol and device drivers are not tied to any specific commercial platform, either. Thus, the IP cores and software codes are portable and can be reused for different FPGA devices and prototyping boards. • “Upward compatible. ” The development follows rigorous and proven design principles and practices. These knowledge and skills can be applied in the future for more complicated commercial platforms and larger projects. In fact, the IP cores and drivers developed can be easily modified to be incorporated into existing commercial IP frameworks.

FPro System (cont. ) FPGA Prototyping” or “Fun and Professional • Fun. It can incorporate existing I/O modules and quickly develop a functional prototyping project. It can provide hardware acceleration capability and thus is more capable and more flexible than any microprocessor board. This give us an opportunity to develop interesting and challenging projects and make studying hardware more “fun”.

Platform Hardware Organization • Processor module • 32 -bit-wide data path • 32 -bit memory address space • Memory-Mapped-I/O scheme for I/O access • FPro bridge and FPro bus • simple synchronous bus protocol for the two subsystems • MMIO (memory mapped I/O) subsystem • the memory and registers of the I/O peripherals are mapped to the same address space • accessing memory and I/O peripherals involves the same instructions • Video subsystem • coordinates the operation of video cores

Top-level diagram of an FPro system

MMIO Subsystem • Includes a standard slot interface that conforms to the FPro bus protocol • The MMIO subsystem consists of a controller to select a specific slot and can accommodate up to 64 instantiated cores • After being “wrapped” with an interface circuit, custom digital logic can be plugged into the FPro platform. • About a dozen IP cores have been developed and integrated into the MMIO subsystem.

Video Subsystem • Establishes a framework to coordinate the operation of video cores. • A video core generates or processes the video data stream. • The cores are arranged as a cascading chain. • The data stream is pipelined and “blended” through each stage and eventually displayed on a VGA monitor. • The video subsystem demonstrates the principles of handling stream data, in which data are generated continuously and passed through a chain of components for processing.

Software hierarchy of an FPro So. C system

Platform Software Organization • • A simple bare metal software scheme No operating system The processor boots directly into an infinite main loop Software hierarchy of an FPro system contains a hardware layer, a driver layer, and an application layer • A boot routine is associated with the processor. It performs the basic initialization process, such as clearing the caches, configuring the stack and heap segments, and initializing the interrupt, and then transfers control to the main program. • The timer core and UART maintain a system time and assist displaying a debug message on the console.

FPro So. C Development Flow

Modified Development Flow • In Step 3, only the processor module, which contains a processor core and RAM, is generated via the IP integration utility. We must manually construct the HDL code for the toplevel system, which is composed of the instantiation of the previously generated processor module and the MMIO and video subsystems from Step 2. • In Step 6, since only the processor module configuration is listed in the hardware specification file, only processor-related codes, such as the boot routine, will be included in the BSP library. We must manually examine the IP cores in the toplevel HDL file and include the corresponding driver files in the application software project.

Modified Development Flow • Since the processor module is the same most of the time, Steps 1 and 6 only need to be executed once. The generated HDL files and BSP library can be use in subsequent designs.

Vanilla FPro System (Part II of the Textbook)