ECE 426 VLSI System Design Lecture 10 Communicating

ECE 426 - VLSI System Design Lecture 10 - Communicating ASMs March 3, 2003 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette. edu 3/3/03 Lecture 10 - Handshaking 1

Where we are. . . } Last Time } ASM Diagrams } Discuss Lab 5 } Today - Register Transfer Design } Handshaking } FIFOs 3/3/03 Lecture 10 - Handshaking 2

Handshaking } Basic Idea: } Receiver performs “action” at request of sender • Transfer data • Perform a sub-computation } Want action to be performed once for each request } Types of Handshaking } } 1 -way 2 -way 3 -way 4 -way (fully interlocked) 3/3/03 Lecture 10 - Handshaking 3

Goals of Handshaking } Reliably Pass Control Information between ASMs } Reliably Pass Data Between Interacting ASMs } ASMs may be driven by different clocks! S DO_CMD clk 1 R clk 2 DATA 3/3/03 S R clk 1 clk 2 Lecture 10 - Handshaking 4

1 -Way Handshake } R waits for CMD before starting action } S asserts CMD to start action SCMD S CMD R RWAIT S 1 CMD SN-2 CLK R 1 CMD S State CMD F T SN-1 SCMD S 1 S 2 R State RWAIT R 1 R 2 3/3/03 SN SN Lecture 10 - Handshaking RM 5

1 -way Handshake: Observations } Not reliable - why? } Receiver can “miss” assertion of CMD if it isn’t in RWAIT } Receiver may see assertion of CMD twice if it runs on a faster clock than sender 3/3/03 Lecture 10 - Handshaking 6

2 -Way Handshake 1. Sender asserts CMD and waits for ACK before continuing 2. Receiver waits for CMD and then asserts ACK SCMD S CMD R RWAIT ACK F CMD CLK SN-2 CMD ACK S State CMD R 1 SN SCMD R State RWAIT 3/3/03 SCMD S 1 R 2 SN Lecture 10 - Handshaking T ACK SN-1 F RM 7

2 Way Handshake - Observations } Reliable if S and R use same clock } Not reliable if S and R use different clocks } R could see CMD twice if R faster than S } S could see ACK twice if S faster than R 3/3/03 Lecture 10 - Handshaking 8

3 -Way Handshake 1. 2. 3. Sender asserts CMD and waits for ACK before continuing Receiver waits for CMD and then asserts ACK Receiver waits for CMD=0 before continuing SCMD S CMD R ACK F CLK CMD RW 1 ACK S 1 T ACK CMD RW 2 ACK S State F T ACK SN R State RWAIT SCMD S 1 S 2 RW 1 RW 2 R 1 CMD’ CMD SN R 1 3/3/03 SN-2 Lecture 10 - Handshaking T F 9

3 -Way Handshake - Comments } Use in some asynchronous bus interfaces } Not reliable if S is faster than R (see ACK twice) 3/3/03 Lecture 10 - Handshaking 10

4 -Way Handshake (Fully Interlocked) 1. 2. 3. 4. Sender asserts CMD and waits for ACK before continuing Receiver waits for CMD and then asserts ACK Receiver waits for CMD=0 before continuing SC 1 Sender waits for ACK=0 before continuing CMD S F R ACK CMD RW 1 ACK SC 2 T ACK CMD CLK CMD RW 2 T T ACK ACK CMD’ S State SC 1 SC 2 R State RW 1 RW 2 R 1 3/3/03 CMD SN ACK’ Lecture 10 - Handshaking F R 1 T F 11

4 -Way Handshaking } Works under all circumstances } Still need synchronizers if clocks are different! CMD S R ACK clk 1 clk 2 3/3/03 Lecture 10 - Handshaking 12

Handshaking with Multiple Clocks } CMD, ACK must be synchronized! } Penalty: even more latency! CMD. s 2 DQ DQ S R QD ACK. s 1 QD ACK clk 1 3/3/03 clk 2 Lecture 10 - Handshaking 13

Handshaking ASMs with Different Clocks } Treat signals passing between S and R as asynchronous! } Important: never try to handshake on multiple bits } Use synchronizers when crossing clock domains 3/3/03 Lecture 10 - Handshaking 14

Alternative to Handshaking: FIFOs } FIFO = First In / First Out Buffer } S writes data once each clock cycle unless FULL } R reads data once every clock cycle unless EMPTY FULL EMPTY S R SCLK 3/3/03 RCLK Lecture 10 - Handshaking 15

FIFO Implementation - Software } Head pointer - marks where to add data } Tail pointer - marks where to remove data } Exceptional conditions: FULL, EMPTY 0 x 0 Write Pointer (Head) 9 7 5 Head Pointer EMPTY FULL 0 x 7 Array (RAM) 3/3/03 Lecture 10 - Handshaking 16

FIFO Implementation - Hardware } Q: How do we calculate FULL & EMPTY? Dual-Port RAM FULL DATA TAIL Write Logic WR WDATA WADDR RDATA RADDR CLK 1 3/3/03 EMPTY HEAD Read Logic DATA CLK 2 Lecture 10 - Handshaking 17

FIFO Implementation - Hardware } Q: How do we calculate FULL & EMPTY? } A: Must compare head & tail pointers Dual-Port RAM FULL DATA TAIL Write Logic WR WDATA WADDR RDATA RADDR CLK 1 3/3/03 EMPTY HEAD Read Logic DATA CLK 2 Lecture 10 - Handshaking 18

FIFO Implementation - Hardware } Problem: } Read logic (clk 1) needs to see Tail pointer (clk 2) } Write logic (clk 2) needs to see the Head pointer (clk 1) } Proposed Solution: } Synchronize Head, Tail } Problem again! Multiple bits in Head, Tail } Synchronization won’t work on multiple bits! } Complete Solution: } Use Gray Code for Head, Tail (only 1 bit changes at a time!) } Translate to/from binary internally 3/3/03 Lecture 10 - Handshaking 19

Coming Up } Timing w/ Design Compiler } Discuss Project 3/3/03 Lecture 10 - Handshaking 20

Alternative - Buffering with a FIFO } FIFO = First in First Out Buffer 3/3/03 Lecture 10 - Handshaking 21

Synchronization Problems 3/3/03 Lecture 10 - Handshaking 22

Coming Up: } Multiple Controller / Datapath Designs } Synchronization Issues with Multiple Controllers 3/3/03 Lecture 10 - Handshaking 23

Verification Plan } Definition: A Specification of the Verification Effort } Prerequisite: Specification document for design } Defnining Success - Must Identify } Features which must be exercisedunder which conditions } Expected Response 3/3/03 Lecture 10 - Handshaking 24

Levels of Verification } } Board System / Subsystem ASIC / FPGA Unit / Subunit 3/3/03 Lecture 10 - Handshaking 25

Levels of Verification } } Connectivity Transaction / Cooperative Data Flow Functionality Ad Hoc } Designer verifies basic functionality 3/3/03 Lecture 10 - Handshaking 26

Levels of Verification - Notes } Stable interfaces required at each level of granularity 3/3/03 Lecture 10 - Handshaking 27

System Design Issues } } ASM Diagrams Synchronization & Metastability Handshaking Working with Multiple Clocks 3/3/03 Lecture 10 - Handshaking 28

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