ECE 232 Hardware Organization and Design Lecture 16

ECE 232 Hardware Organization and Design Lecture 16 Microprogrammed Control Maciej Ciesielski www. ecs. umass. edu/ece/labs/vlsicad/ece 232/spr 2002/index_232. html ECE 232 L 16. Microprog. 1 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Outline ° Review • FSM-based control • Structured control logic ° Microprogramming • Basic concept – sequencing control • Designing a microinstruction code • Variations: horizontal vs. vertical microprogram ° Overview of control • State machine vs. microprogram ECE 232 L 16. Microprog. 2 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

The Big Picture: Where are We Now? ° The Five Classic Components of a Computer Processor Input Control Memory Datapath Output ° Today’s Topics: microprogrammed control ECE 232 L 16. Microprog. 3 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Controller Design ° The state diagrams that define the controller for an instruction set processor are highly structured ° Use this structure to construct a simple “microsequencer” ° Control reduces to programming this very simple device • microprogramming sequencer control datapath control microinstruction micro-PC ECE 232 L 16. Microprog. 4 sequencer Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Example: Jump-Counter i 0000 i i+1 Zero Increment op-code Map ROM Counter ECE 232 L 16. Microprog. 5 Load Adapted from Patterson 97 ©UCB zero inc load Copyright 1998 Morgan Kaufmann Publishers

Using a Jump Counter IR <= MEM[PC] 0000 inc A <= R[rs] B <= R[rt] S <= A fun B 0100 inc ORi S <= A or ZX 0110 inc LW S <= A + SX 1000 inc M <= MEM[S] 1001 inc R[rd] <= S R[rt] <= M PC <= PC + 4 0101 zero ECE 232 L 16. Microprog. 6 0111 zero inc SW BEQ & ~Equal BEQ & Equal S <= A + SX 1011 inc MEM[S] <= B PC <= PC + 4 PC <= PC + SX || 00 0011 zero 0010 zero 1100 zero 1010 zero Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers Write-back Execute Memory R-type “decode” 0001 load “instruction fetch”

Our Microsequencer taken (from IR) Datapath control ZIL Micro-PC op-code Z = zero I = increment L = load (branch) Map ROM ECE 232 L 16. Microprog. 7 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Microprogram Control Specification µPC Taken 0000 0001 0010 BEQ 0011 R: 0100 0101 ORi: LW: SW: Next IR PC Ops Exec Mem Write-Back en sel A B Ex Sr ALU S R W M M-R Wr Dst ? inc 1 0 load 1 inc x zero 1 1 x zero 1 0 x inc 0 1 fun 1 x zero 1 0 0 1 1 0110 0111 x x inc zero x x inc zero 0 0 or 1 1 0 0 1000 1001 1010 1 1011 1100 ECE 232 L 16. Microprog. 8 1 0 add 1 1 0 0 1 0 Adapted from Patterson 97 ©UCB 1 0 add 1 0 1 Copyright 1998 Morgan Kaufmann Publishers

How Effectively are we utilizing our hardware? IR <- Mem[PC] A <- R[rs]; B<– R[rt] S <– A + B R[rd] <– S; PC <– PC+4; S <– A or ZX R[rt] <– S; PC <– PC+4; S <– A + SX M <– Mem[S] <- B R[rd] <– M; PC <– PC+4; PC < PC+SX; ° Example: memory is used twice, at different times • Avg. mem access per inst = 1 + Flw + Fsw ~ 1. 3 • if CPI is 4. 8, Instr-mem utilization = 1/4. 8, Data-mem = 0. 3/4. 8 ° We could reduce HW without hurting performance • extra control ECE 232 L 16. Microprog. 9 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

“Princeton” Organization (von Neumann) A-Bus B Bus next PC P C IR ZX SX Reg File A B S Mem W-Bus ° Single memory for instruction and data access • memory utilization -> 1. 3/4. 8 ° In this case our state diagram does not change • several additional control signals • must ensure each bus is only driven by one source on each cycle ECE 232 L 16. Microprog. 10 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Alternative datapath (book): Multiple Cycle Datapath ° Minimizes hardware: 1 memory, 1 adder PCWr. Cond Zero Mem. Wr IRWr 1 Wr. Adr 32 Din Dout 32 32 Rt 0 5 Rd Rb bus. A Reg File 32 bus. W bus. B 32 1 Extend Ext. Op Adapted from Patterson 97 ©UCB 32 1 Rw 1 Mux 0 Imm 16 ECE 232 L 16. Microprog. 11 Ra << 2 4 Zero 0 1 32 ALU Out 1 32 Mux Ideal Memory Rt 5 Target ALU Mux RAdr Rs 32 0 0 Mux 0 Instruction Reg 32 32 ALUSel. A Reg. Wr 32 PC 32 Reg. Dst Br. Wr Mux Ior. D PCSrc 32 2 3 32 ALU Control ALUOp Memto. Reg ALUSel. B Copyright 1998 Morgan Kaufmann Publishers

Our Controller FSM Spec IR <= MEM[PC] PC <= PC + 4 0000 “instruction fetch” “decode” A <= R[rs] B <= R[rt] S <= A fun B 0100 ORi S <= A op ZX 0110 LW S <= A + SX 1000 BEQ SW S <= A + SX 1011 S <= A - B 0010 Equal M <= MEM[S] 1001 R[rd] <= S 0101 ECE 232 L 16. Microprog. 12 R[rt] <= S 0111 MEM[S] <= B 1100 ~Equal PC <= PC + SX || 00 0011 R[rt] <= M 1010 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers Write-back R-type Memory Execute 0001

Microprogramming ° Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: • A particular strategy for implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: • Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance ECE 232 L 16. Microprog. 13 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

FSM-based Control Unit Inputs PS OP to Multi-cycle Datapath Outputs Combinational logic unit NS State Reg Next state Inputs from Instruction Register OPcode field ECE 232 L 16. Microprog. 14 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Control Logic Outputs Sequencer-based Control Unit Multi-cycle Datapath Inputs 1 Types of “branching” Adder State Reg Address Select Logic • Set state to 0 • Dispatch (state 1) • Use incremented state number Opcode ECE 232 L 16. Microprog. 15 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

“Macroinstruction” Interpretation Main Memory ADD SUB AND . . . DATA execution unit CPU control memory ECE 232 L 16. Microprog. 16 User program plus data this can change! each of these is mapped into one of these AND microsequence e. g. , Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Variations on Microprogramming ° “Horizontal” Microcode – control field for each control point in the machine µseq µaddr A-mux B-mux bus enables register enables ° “Vertical” Microcode – compact microinstruction format for each class of microoperation – local decode to generate all control points branch: µseq-op µadd execute: ALU-op A, B, R memory: mem-op S, D Horizontal Vertical ECE 232 L 16. Microprog. 17 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Extreme Horizontal 3 1. . . 1 bit for each loadable register enb. MAR enb. AC. . . N 3 N 2 N 1 N 0 input select Incr PC ALU control • Potential for error: may generate wrong control combinations (transfers that can never happen at the same time). • Makes sense to encode fields to save ROM space Example: mem_to_reg and ALU_to_reg should never happen simultenously; => encode in single bit which is decoded rather than two separate bits NOTE: encoding should be such that parallel actions supported by datapath should be specifiable in a single microinstruction ECE 232 L 16. Microprog. 18 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

More Vertical Format src dst D E C other control fields next states inputs D E C MUX Some of these may have nothing to do with registers! Multiformat Microcode: 6 1 3 0 cond 1 1 3 dst D E C ECE 232 L 16. Microprog. 19 next address 3 src 3 alu Branch Jump Register Xfer Operation D E C Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Hybrid Control Not all critical control information is derived from control logic E. g. , Instruction Register (IR) contains useful control information, such as register sources (RS), destinations, opcodes, etc. enable signals from control IR op to control ECE 232 L 16. Microprog. 20 R S 1 R S 2 R D D E C rs 1 rs 2 Register File rd Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Horizontal vs. Vertical Microprogramming NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: • horizontal organization (1 control bit per control point) • vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal Vertical + more control over the potential parallelism of operations in the datapath + easier to program, not very different from programming a RISC machine in assembly language - uses up lots of control store ECE 232 L 16. Microprog. 21 Adapted from Patterson 97 ©UCB - extra level of decoding may slow the machine down Copyright 1998 Morgan Kaufmann Publishers

Designing a Microinstruction Set 1. Start with list of control signals 2. Group signals together that make sense: create “fields” 3. Places fields in some logical order (e. g. , ALU operation & ALU operands first and microinstruction sequencing last) 4. Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals 5. To minimize the width, encode operations that will never be used at the same time ECE 232 L 16. Microprog. 22 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

1+2. Start with list of control signals, grouped into fields Multiple Bit Control Single Bit Control Signal name Effect when deasserted Effect when asserted ALUSel. A 1 st ALU operand = PC 1 st ALU operand = Reg[rs] Reg. Write None Reg. is written Memto. Reg. write data input = ALU Reg. write data input = memory Reg. Dst Reg. dest. no. = rd Target. Write None Target reg. = ALU Mem. Read None Memory at address is read Mem. Write None Memory at address is written Ior. D Memory address = PC Memory address = ALU IRWrite None IR = Memory PCWrite None PC = PCSource PCWrite. Cond None IF ALUzero then PC = PCSource ALUOp ALUSel. B PCSource ECE 232 L 16. Microprog. 23 00 01 10 11 000 001 010 011 100 00 01 10 ALU adds ALU subtracts ALU does function code ALU does logical OR 2 nd ALU input = Reg[rt] 2 nd ALU input = 4 2 nd ALU input = sign extended IR[15 -0] 2 nd ALU input = sign extended, shift left 2 IR[15 -0] 2 nd ALU input = zero extended IR[15 -0] PC = ALU PC = Target PC = PC+4[29 -26] : IR[25– 0] << 2 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Start with list of control signals, cont’d • Called “micro. PC” or “µPC” vs. state register Datapath ° For next state function (next microinstruction address), use sequencer-based control unit Sequencing Microcode storage (ROM) 1 micro. PC Adder Signal Effect 00 next µaddress = 0 01 next µaddress = dispatch ROM 10 next µaddress = µaddress + 1 Mux 2 1 µaddress Select Logic 0 0 ROM Opcode ECE 232 L 16. Microprog. 24 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

3. Microinstruction Format: unencoded vs. encoded fields Field Name Width Control Signals Set wide narrow ALU Control 4 2 ALUOp SRC 1 2 1 ALUSel. A SRC 2 5 3 ALUSel. B ALU Destination Target. Wr. 6 4 Memory 4 3 Mem. Read, Mem. Write, Ior. D Memory Register 1 1 IRWrite PCWrite Control PCSource 5 4 PCWrite, PCWrite. Cond, Sequencing 3 2 Addr. Ctl Total width 30 20 bits ECE 232 L 16. Microprog. 25 Adapted from Patterson 97 ©UCB Reg. Write, Memto. Reg, Reg. Dst, Copyright 1998 Morgan Kaufmann Publishers

4. Legend of Fields and Symbolic Names Field Name Field values Field function with specific value ALU Add ALU adds Subt. ALU subtracts Func code ALU does function code Or ALU does logical OR SRC 1 PC 1 st ALU input = PC rs 1 st ALU input = Reg[rs] SRC 2 4 2 nd ALU input = 4 Extend 2 nd ALU input = sign ext. IR[15 -0] Extend 0 2 nd ALU input = zero ext. IR[15 -0] Extshft 2 nd ALU input = sign ex. , sl IR[15 -0] rt 2 nd ALU input = Reg[rt] ALU destination Target = ALUout rd Reg[rd] = ALUout Memory Read PC Read memory using PC Read ALU Read memory using ALU output Write ALU Write memory using ALU output Memory register IR IR = Mem Write rt Reg[rt] = Mem Read rt Mem = Reg[rt] PC write ALU PC = ALU output Target-cond. IF ALU Zero then PC = Target jump addr. PC = PCSource Sequencing Seq Go to sequential µinstruction Fetch Go to the first microinstruction Dispatch using ROM. ECE 232 L 16. Microprog. 26 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Overview of Control ° Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Control Function Explicit Next State + Dispatch ROMs Microprogram counter Logic Representation Logic Equations. Truth Tables Implementation PLA technique ROM ECE 232 L 16. Microprog. 28 “hardwired control” Adapted from Patterson 97 ©UCB “microprogrammed control” Copyright 1998 Morgan Kaufmann Publishers

Microprogramming Pros and Cons ° Ease of design ° Flexibility • Easy to adapt to changes in organization, timing, technology • Can make changes late in design cycle, or even in the field ° Can implement very powerful instruction sets (just more control memory) ° Generality • Can implement multiple instruction sets on same machine. • Can tailor instruction set to application. ° Compatibility • Many organizations, same instruction set ° Costly to implement ° Slow ECE 232 L 16. Microprog. 29 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers

Summary ° Specialize state-diagrams easily captured by microsequencer • simple increment & “branch” fields • datapath control fields ° Control design reduces to Microprogramming ° Exceptions are the hard part of control – to be discussed later ° Need to find convenient place to detect exceptions and to branch to state or microinstruction that saves PC and invokes the operating system ° As we get pipelined CPUs that support page faults on memory accesses which means that the instruction cannot complete AND you must be able to restart the program at exactly the instruction with the exception, it gets even harder ECE 232 L 16. Microprog. 30 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers