ECE 224 a CMOS VLSI Design Lab F

ECE 224 a CMOS VLSI Design Lab F. Brewer © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

ECE 224 a Fabricate a real design q MMI/Cadence/Mentor/Synopsys Tools q § MMI Full Custom (Cell, Array, Data-Path) § Cadence/Synopsys P&R (digital path) q Not a first class in VLSI § 124 a or equivalent required, 124 d is good plan q Review Essential Concepts § FET, Diode, Transient Model (Elmore), Sizing § Layout/Design Rules: Wire Planning, Gradient Variation, Tricks of Trade © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Class Logistics q Homework (out wed, due 1 week) q Quizzes (3 in-class) q No Final q Design Proposal q Design Review q Submitted Project Report © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

The First Integrated Circuits Bipolar logic 1960’s ECL 3 -input Gate Motorola 1966 © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

ECE 224 a Project q 0. 6 um 3 M § § q 3. 3 -5 V bulk CMOS P 1/P 2 CAP Poly Resistor HV Implants (up to 40 V!) 2. 25 mm 2 § 1. 5 mmx 1. 5 mm q 9 week design cycle, 3 person © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Current State of Affairs q High-End Technology (32 -22 nm) still a driver § Limited to large design efforts ($$$NRE) § Small number of Players – – q FPGA: Actel, Lattice, Xilinx, Altera Processor: AMD, Intel, IBM SOC: Conexant, Cisco, Juniper, Nintendo… Structured ASIC: NEC, Fujitsu, Hitatchi, Samsung Most Design Starts > 0. 09 um! § Mixed Signal Applications § Mature Technology – Lower NRE and Risk § High Potential for Innovative Design/Architecture © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

224 a Project Limits q Get § § § 1 1. 5 x 1. 5 mm design/2 -3 students 1500 Standard Cell Gates 50 kbits ROM/5 kbits SRAM 64 Comparators/ 15 Op-Amps 40 -48 pins (at least 8 used for Pwr/Gnd) 100 Mhz practical large swing (3. 3 V) limit – 800+MHz differential 300 m. V § 3. 3 or 5 V default, 12 V possible © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Design Schedule q 9 § § § week design flow 1 week project definition 3 weeks schematic/simulation + test design 2 weeks layout 2 weeks design verification and tweak Tape Out – Must be DRC, LVS Clean – Must have Full Die Simulation/Sanity – Must have test plan and agree to physical test © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Survival Guide q Choose Team to Complement Skills! § No more than 3. 2 is fine, 1 if enough project slots q Under-Specify/Over-Deliver § If you cannot finish basic design in 1 week simplify design! § Basic Design through layout before adding features! § Make decisions early, stick to them § Use expert resources: Professors, experienced students q Goal: Have Fun! -- © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

What to make? q Mixed Signal Designs Rock § Pure Digital 1 -bit signal processing § Analog Sensors/Digital Output Good Choice – Temperature, Light, Magnetic, RF, Field, voltage, current, time, phase… § Digital Synthesis/Power also good – Sound (even music!), RFID/Xmit, motor driver/controller, PLL (clock synthesis or other…), Display (LCD) or LED § Tricky Small Designs – Journal of Consumer Circuits, JSSC about 10 -15 years ago (0. 5 um in vogue), LFSR tricks… © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

What to NOT make: q Micro. Processor § 4 -bit possible (8 bit tiny MIPS – won’t fit w/o reg) – 1 success in 22 years, 5 months design time § No non-volatile Memory – (design some is good, but hard, project!) q Digital Multiplier/Adder/Function Block § Space, Pins (How to test!), Why? q Generic Op. Amp § How to test/characterize? § If you have a use in mind – it is not generic! © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Design Methodology © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Evolution in Complexity © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

The Design Productivity Challenge 100, 000 10, 000 58%/Yr. compound Complexity growth rate 1, 000 100, 000 1, 000 Productivity growth rate 10 100 21%/Yr. compound Produc 2009 2005 2001 1997 1993 1989 1985 Logic Transistors per Chip (K) Productivity (Trans. /Staff-Month) 100, 000 10, 000 1981 Logic Transistors per Chip (K) 1, 000 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 A growing gap between design complexity and design productivity Source: ITRS’ 97 © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Scaling? Technology shrinks by 0. 7/generation q With every generation can integrate 2 x more functions per chip; chip cost does not increase significantly q Cost of a function decreases by 2 x q But … q § How to design chips with more and more functions? § Design engineering population does not double every two years… § Physical design constraints more and more difficult to surmount § Diminishing Returns for Design Dollars © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

The Custom Approach Intel 4004 © Digital Integrated Circuits 2 nd and F. Brewer Intel 2003, 2011 Courtesy Design Methodology

Transition to Automation and Regular Structures Intel 4004 (‘ 71) Intel 80286 Intel 8080 Intel 8085 Intel 80486 © Digital Integrated Circuits 2 nd and F. Brewer Intel 2003, 2011 Courtesy Design Methodology

Automating Design q Exploitation By Algorithms § Regular Structures § Logic Synthesis § Regularization of Connection q Floorplanning (Localization of function) § System Level Performance/Power/Cost § Allocation of Physical Resources q Communication/Interconnect § Hierarchy based on Sensitivity to Latency § Wires to Link Protocols © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

A System-on-a-Chip: Example Courtesy: Philips © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Design Methodology • Design process traverses iteratively between three abstractions: behavior, structure, and geometry • Trick: automate these steps © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Implementation Choices Digital Circuit Implementation Approaches Custom Semi-custom Array-based Pre-diffused (Gate Arrays) Hard Macros (RAM/ROM) Cell-based Standard Cells Compiled Cells Macro Cells Pre-wired (FPGA's) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Implementation Strategies q Data-Path § 1 D tiling, custom in depth q Cell based logic § Technology confined to cells (area) § 2 D via 1 D cell rows, automatic P&R q 2 D Arrays (Memory, CAM, CCD, MPY) § Dense but very constrained § Design time consuming! © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

2 -d Cell Based: “Hard” Modules 256 32 (or 8192 bit) SRAM Generated by hard-macro module generator © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

1 -d Cell-based Design (standard cells) Feedthrough cell Logic cell Routing channel Rows of cells Functional module (RAM, multiplier, ) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Routing channel requirements are reduced by presence of more interconnect layers Design Methodology

Concepts of Placement q Standard cells are placed in “placement rows” q Cells in a timing-critical path are placed close together to reduce routing related delays (Timing Driven) q Placement rows can be abutting or non-abutting © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Concepts of Routing q Connecting between metal layers requires one or more “vias” q Metal Layers have preferred routing directions § Metal 1 (Blue) Horizontal § Metal 2 (Yellow) Vertical § Metal 3 (Red) Horizontal © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Concept of Routing Tracks q Metal routes must meet minimum width and spacing “design rules” to prevent open and short circuits during fabrication q In grid based routing systems, these design rules determine the minimum center-to-center distance for each metal layer (Track/Grid spacing) q Congestion occurs if there are more wires to be routed than available tracks © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Grid-Based Routing System q Metal traces (routes) are built along and centered around routing tracks q Each metal layer has its own tracks and preferred routing direction § Metal 1 – Horizontal § Metal 2 – Vertical q Track and pitch information can be located in the technology file § Design Rules © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Standard Cell — Old Example q Automation § Height fixed § Width variable § Channel routing q Optimization § Place by annealing to minimize wirelength and net criticality [Brodersen 92] © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Standard Cell – The New Generation Cell-structure hidden under interconnect layers Same basic scheme -- more layers -- wires over cells -- power/clock plan -- leave spaces for Filler/bypass and Buffer cells © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Standard Cell - Example 3 -input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

“Soft” Macro. Modules Synopsys Design. Compiler © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Gate Array — Sea-of-gates Uncommited Cell Committed Cell (4 -input NOR) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Sea-of-gate Primitive Cells Using oxide-isolation Using gate-isolation © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA 300 K (0. 6 mm CMOS) © Digital Integrated Circuits 2 nd and F. Brewer Courtesy LSI 2003, Logic 2011 Design Methodology

The return of gate arrays? Via programmable gate array (VPGA) Via-programmable cross-point metal-5 metal-6 programmable via Exploits regularity of interconnect [Pileggi 02] © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Pre-wired Arrays: Classification of prewired arrays (or fieldprogrammable devices): q Based on Programming Technique § Fuse-based (program-once) § Non-volatile EPROM based § RAM based q Programmable Logic Style § Array-Based § Look-up Table q Programmable Interconnect Style § Channel-routing § Mesh networks © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Fuse-Based FPGA antifuse polysilicon ONO dielectric n+ antifuse diffusion 2 l Open by default, closed by applying current pulse © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 From Smith’ 97 Design Methodology

Array-Based Programmable Logic I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array Programmable AND array I 3 I 2 I 1 I 0 Programmable OR array Fixed AND array O 3 O 2 O 1 O 0 PLA (flexible – sizing) I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array Programmable AND array O 3 O 2 O 1 O 0 PROM (dense) O 3 O 2 O 1 O 0 PAL (uniform load) Indicates programmable connection Indicates fixed connection © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Programming a PROM 1 X 2 X 1 X 0 : programmed node NA NA f 1 f 0 © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Rent’s Rule q Rent described a relation between the number of components in a subsystem and the number of wires to connect it. q The rule was developed for large digital systems, but is reflected in all human design (hierarchy) A Rent coefficient of 0. 5 corresponds to a planar scalable design – i. e. the perimeter (where wires go) is grows to support the area of a planar figure. q © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Rent’s Rule: 10, 000 high performance computers board level 1, 000 r=0. 5 K=1. 9 gate arrays chip level 100 microprocessors r=0. 63 K=1. 4 r=0. 45 K=0. 82 r=0. 12 K=6 static ram 10 100 dynamic ram 1, 000 100, 000 1, 000 1987] Design Methodology © Digital Integrated Circuits 2 nd and F. Brewer 2003, [Bakoglu, 2011

Design Flow © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Design Flow - Overview q Generic VLSI Design Flow from System Specification to Fabrication and Testing q Steps prior to Circuit/Physical design are part of the FRONT-END flow q Physical Level Design is part of the BACKEND flow § Physical Design is also known as “Place and Route” q CAD tools are involved in all stages of VLSI design flow § Different tools can be used at different stages due to EDA common data formats* © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Where does the Gate Level Netlist come from? © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Floorplanning q 2 D layout: § Area does not correspond to architecture § Communication on boundaries – wire length © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Design Must Be Floorplanned Before P&R q Floorplan of design: § Core area defined with large macros placed § Periphery area defined with I/O macros placed § Power and Ground Grid (Rings and Straps) established q Utilization: § Percentage of the core used by placed standard cells and macros typically 80 -85% © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

I/O Placement and Chip Package Requirements q Some Bond Wire requirements: § No Crossing § Minimum Spacing § Maximum Angle § Maximum Length © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Guidelines for a Good Floorplan q. A few quick iterations of place and route with timing checks may reveal the need for a different floorplan © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Defining the Power/Ground Grid and Blockages q Purpose of Grid is to take the VDD and VSS received from the I/O area and distribute it over the core area q Blockages can also be added in the floorplan to prohibit standards cells from being placed in those areas q Loading IR drop and noise issues q Sometimes need Guard rings around critical regions © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Design Flow – Timing Driven Placement q Astro™ optimizes, places, and routes the logic gates to meet all timing constraints q Balancing § § design requirements Timing Area Power Signal Integrity © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Timing Constraints q Astro™ needs constraints to understand the timing intentions § Arrival time of inputs § Required arrival time at outputs § Clock period q Constraints come from the Logic Synthesis tool § SDC (Synopsys Design Constraints) format © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Cell and Net Delays q Astro™ calculates delay for every cell and every net q To calculate delays, Astro™ needs to know the resistance and capacitance of each net § Uses geometry of net and Look Up Tables to estimate the resistances and capacitances © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Timing Driven Placement q Timing Driven Placement places critical path cells close together to reduce net RC q Prior to routing, RC are based on Virtual Routes q What if critical paths do not meet timing constraints with placement? © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Logic Optimizations q These optimizations can be done during pre-place, in-place, or post-place stages of placement q Each optimization can be done separately or all done concurrently during placement (none – all) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

The “Design Closure” Problem Iterative Removal of Timing Violations (white lines) Problem: no guarantee of convergence, can take weeks Synopsys © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Timing Closure and Mask Verification RTL ECO Constraint, Library ECO Density, Order ECO Fail Timing © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Design Flow – Clock Tree Synthesis q All clock pins are driven by a single clock source q Large delay and transition time due to length of net q Clock signal reach some registers before others (Skew) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

After Clock Tree Synthesis q. A clock (buffer) tree is built to balance the output loads and minimize the clock skew q. A delay line can be added to the network to meet the minimum insertion delay (clock balancing) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Gated - CTS q Clocks may not be generated directly from I/O q Power saving techniques such as clock-gating are used to turn of the clock to sections of the design © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Effects of CTS q Several (Hundreds/Thousands) of clock buffers added to the design q Placement / Routing congestion may increase q Non-clock cells may have been moved to less ideal locations q Timing violations can be introduced © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Timing Driven Routing q Routing along the timing-critical path is given priority § Creates shorter, faster connections q Non-critical paths are routed around critical areas § Reduces routing congestion problems for critical paths § Does not adversely impact timing of non-critical paths © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Timing Verification q Calibre PEX performs the layout parasitic extraction of the resistances and capacitances of all wires and devices in the design q Results in Augmented Spice Deck and in logic format decks such as SPEF (Standard Parasitic Extended Format) § SPEF is an extended form of Standard Parasitic Format (SPF), which enables the transfer of design specific resistances and capacitances from physical design to timing analysis and simulation tools q Primetime performs static timing analysis § Detects timing violations by combining SPEF and netlist and checks against the design timing constraints (setup and hold times) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Physical Verification q Checks the design for fabrication feasibility and physical defects that could result in the design to not function properly § 3 checks (DRC/ERC, and LVS) q Design Rule Checks (DRC) § Verifies that design does not violate any fabrication rules associated with the target process technology (metal width/space, antenna wires, fill ratio, etc) q Electrical Rules Checks (ERC) § Verifies that there are no short or open circuits with power and ground as well as resistors/capacitors/transistors with floating nodes (part of LVS) q Layout Versus Schematic (LVS) § Final physical design matches the logical (schematic) version in terms of correct connectivity and number of electrical devices © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

Fabrication q Physical Design process is complete upon successful completion of timing, functional, and physical verification q The design can be “Taped-Out” and GDSII created for the manufacturer § GDSII (Graphic Design System II) is a binary format containing the physical geometry information of the design. § The shapes are assigned numeric attributes in the form of “Layer Number” and “Data Type” (Metal 1 => 100: 0) q Fabrication and Test determine which chips can be implemented into the system (yield) © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

UCSB Tools q Tools from all the major vendors: § Cadence (ON-Semi 0. 6 um via NCSU/OSU SCMOS) § Synopsys (Logic Synthesis, Simulation, Timing) § Mentor (Calibre DRC/LVS/PEX) § MMI (Full Custom, Array and Data. Path) q Final Chip physical verification must be through Calibre full-chip DRC and LVS § Full-chip extracted spice sanity check © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology

HW 1 1. 2. 3. 4. If 6” wafers cost $800/ea, 10” cost $1400 and 12” cost $2000 estimate the die cost of a 5 mmx 5 mm die in each case given a uniform defect rate of 0. 2/cm 2. (Hint: A point defect in your chip kills it). Analog circuits typically lag by several orders of magnitude is scale compared to digital ones. How does this relate to the complexity of composing two analog circuits to make a more complex behavior? FPGA use is growing – in many cases replacing ASIC designs. Typically, such designs are 30 -150 x slower than ASIC designs of the same power. Why? Why is Timing Closure a serious issue in highly constrained digital designs (big, fast, low-power, lots of pins)? © Digital Integrated Circuits 2 nd and F. Brewer 2003, 2011 Design Methodology