ECE 111 Winter 2016 http cwcserv ucsd edubilllinclassesECE

ECE 111, Winter 2016 • http: //cwcserv. ucsd. edu/~billlin/classes/ECE 111/index. php • Professor Bill Lin – Office hours: TBD, 4310 Atkinson Hall • Lectures: – Section A 00: MWF 11 -11: 50 a, WLH 2204 – Section B 00: MWF 12 -12: 50 p, WLH 2204 – Section C 00: MWF 10 -10: 50 a, EBU 1 2315 • No Discussion Sections • TAs: – – – Section A 00: Yang Song and Ping Yin Section B 00: Sidharth Kodaikkal Vijayan and Pranav Marakani Section C 00: Shalini Kedlaya and Praneeth Sanapathi Office hours: TBD Note: You may get help from any of the 6 TAs during their office hours.

Projects • Goal: Learn Verilog-based chip design • Project 1: Simple Fibonacci Calculator – Due 1/22, Pass/No Pass • Project 2: RLE Processor – Due 2/10, Pass/No Pass – Must re-do if not within 20% of average performance • Final Project: SHA 1 Security Processor – Due 3/17 (Wed finals week), grading on performance

Altera Software • See Software Downloads Page http: //cwcserv. ucsd. edu/~billlin/classes/ECE 111/software. php which links to this: http: //dl. altera. com/? edition=web • Quartus Prime Lite Edition for Windows – Quartus Prime Lite Edition (earlier versions were called Quartus II) – Model. Sim-Altera Edition – Arria II device support

Icarus Verilog • Another simulator http: //iverilog. icarus. com • Just runs together with your testbench and prints out whatever is specified in the testbench

More Information • No textbook for this class. Verilog information on class website. Also tutorial examples provided. • This is NOT a lecture-based class. Class time used to talk about Verilog in the beginning, but mostly about project information for the rest of the quarter. • Projects done in teams of 2 students.

Useful Altera Websites • Verilog HDL Basics (50 minutes online course) http: //www. altera. com/education/training/courses/OHDL 1120 • Demonstration Center http: //www. altera. com/education/demonstrations/dem-index. html