Dynamic Scheduling A scheme to overcome data hazards

Dynamic Scheduling A scheme to overcome data hazards EE 524/Cpt. S 561 Advanced Computer Architecture

Advantages of Dynamic Scheduling • Dynamic scheduling - hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior • It handles cases when dependences unknown at compile time – it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve • It allows code that compiled for one pipeline to run efficiently on a different pipeline • It simplifies the compiler • Hardware speculation, a technique with significant performance advantages, builds on dynamic scheduling EE 524/Cpt. S 561 Advanced Computer Architecture

HW Schemes: Instruction Parallelism • Key idea: Allow instructions behind stall to proceed DIVD ADDD SUBD F 0, F 2, F 4 F 10, F 8 F 12, F 8, F 14 • Enables out-of-order execution and allows out-of-order completion (e. g. , SUBD) – In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) • Will distinguish when an instruction begins execution and when it completes execution; between 2 times, the instruction is in execution • Note: Dynamic execution creates WAR and WAW hazards and makes exceptions harder EE 524/Cpt. S 561 Advanced Computer Architecture

Dynamic Scheduling Step 1 • Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue • Split the ID pipe stage of simple 5 -stage pipeline into 2 stages: • Issue—Decode instructions, structural hazards check for • Read operands—Wait until no data hazards, then read operands EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Algorithm • Control & buffers distributed with Function Units (FU) – FU buffers called “reservation stations”; have pending operands • Registers in instructions replaced by values or pointers to reservation stations(RS); called register renaming; – Avoids: WAR RX inst. i WAW hazards RX inst. j – More reservation stations than registers, so can do optimizations compilers cannot • Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs • Load and Stores treated as FUs with RSs as well. • Integer instructions can go past branches, allowing FP ops beyond basic block in FP queue. EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo scheme From memory From instruction unit 6 FP FP 5 4 Load Operation 3 buffers queue Registers Operand buses 2 1 Store 3 buffers 2 1 Operation bus 3 To memory 2 Reservation Stations 2 1 1 FP adders FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Reservation Station Components Op—Operation to perform in the unit (e. g. , + or –) Vj, Vk—Value of Source operands – Store buffers has V field, result to be stored Qj, Qk—Reservation stations producing source registers (value to be written) – Note: No ready flags as in Scoreboard; Qj, Qk=0 => ready – Store buffers only have Qi for RS producing result Busy—Indicates reservation station or FU is busy Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. EE 524/Cpt. S 561 Advanced Computer Architecture

Three Stages of Tomasulo Algorithm 1. Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Execution—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available • Normal data bus: data + destination (“go to” bus) • Common data bus: data + source (“come from” bus) – 64 bits of data + 4 bits of Functional Unit source address – Write if matches expected Functional Unit (produces result) – Does the broadcast EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 0 EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 0 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 LD F 6, 34(R 2) FP Registers Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation 2 Stations 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 1 Load buffers 6 5 4 3 2 1 34+R 2 From instruction unit FP operation queue From memory FP Registers F 6 : load 1 LD F 2, 45(R 3) LD F 6, 34(R 2) Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation 2 Stations 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 2 Load buffers 6 5 4 3 2 45+R 3 1 34+R 2 From instruction unit FP operation queue From memory FP Registers F 2 : load 2 F 6 : load 1 MULTD F 0, F 2, F 4 LD F 2, 45(R 3) LD F 6, 34(R 2) Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation 2 Stations 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 3 Load buffers 6 5 4 3 2 45+R 3 1 Mem[34+R 2] From instruction unit FP operation queue From memory FP Registers F 0 : mult 1 F 2 : load 2 F 6 : load 1 SUB F 8, F 6, F 2 MULTD F 0, F 2, F 4 LD F 2, 45(R 3) LD F 6, 34(R 2) Store buffers Operand buses 3 2 1 Operation bus 3 To memory 2 Reservation 2 Stations 1 FP adders M load 2 “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 4 Load buffers 6 5 4 3 2 Mem[45+R 3] 1 L 1: Mem[34+R 2] From instruction unit FP operation queue From memory FP Registers F 0 : mult 1 F 2 : load 2 DIVD F 10, F 6 F 6 Mem[34+R 2] : load 1 SUB F 8, F 6, F 2 F 8: add 1 MULTD F 0, F 2, F 4 LD F 2, 45(R 3) LD F 6, 34(R 2) Store buffers Operand buses 3 2 1 Operation bus To memory L 1: Mem[34+R 2] 3 2 1 2 Reservation S Mem[34+R 2] load 1 load 2 FP adders Stations M load 2 “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 5 Load buffers 6 5 4 3 2 L 2: Mem[45+R 3] 1 From instruction unit FP operation queue From memory FP Registers F 0 : mult 1 ADD F 6, F 8, F 2 Mem[45+R 3] F 2 : load 2 DIVD F 10, F 6 F 8: add 1 F 10: mult 2 SUB F 8, F 6, F 2 MULTD F 0, F 2, F 4 LD F 2, 45(R 3) Store buffers Operand buses 3 2 1 Operation bus To memory L 2: Mem[45+R 3] 3 Reservation 2 1 S Mem[R 2] load 2 Mem[45+R 3] FP adders Stations D Mult 1 Mem[45+R 3] 2 M Mem[45+R 3] load 2 “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 6 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 ADD F 6, F 8, F 2 F 6: add 2 DIVD F 10, F 6 F 8: add 1 SUB F 8, F 6, F 2 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 A add 1 M[R 3] 1 S Mem[R 2] M[R 3] FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 7 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 ADD F 6, F 8, F 2 F 6: add 2 DIVD F 10, F 6 F 8: add 1 SUB F 8, F 6, F 2 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 A add 1 M[R 3] 1 S Mem[R 2] M[R 3] FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 8 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 ADD F 6, F 8, F 2 F 6: add 2 DIVD F 10, F 6 F 8: F 8 add 1 M()-M() SUB F 8, F 6, F 2 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 A M()-M() add 1 1 S Mem[R 2] M[R 3] FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) Add 1: M()-M() EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 9 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 ADD F 6, F 8, F 2 F 6: add 2 DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 A M()-M() M[R 3] 1 FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 10 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 ADD F 6, F 8, F 2 F 6: add 2 DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 A M()-M() M[R 3] 1 FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 11 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 ADD F 6, F 8, F 2 F 6: F 6 add 2 (M()-m())+M() DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 A M()-M() To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 M[R 3] 1 FP Multipliers FP adders Common data bus (CDB) Add 2: (M()-M())+M() EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 12 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 13 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 14 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 15 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation D Mult 1 M[R 3] 2 Stations M M[R 3] “F 4” 1 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 16 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers F 0 : mult 1 M()*F 4 DIVD F 10, F 6 F 10: mult 2 MULTD F 0, F 2, F 4 Store buffers Operand buses 3 2 1 Operation bus 3 2 1 FP adders To memory Reservation D Stations M M()*F 4 Mult 1 M[R 3] 2 “F 4” 1 FP Multipliers Common data bus (CDB) Mult 1: M()*F 4 EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 17 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers DIVD F 10, F 6 F 10: mult 2 Store buffers Operand buses 3 2 1 Operation bus 3 Reservation 2 To memory D M()*F 4 M[R 3] 1 Stations 1 FP adders 2 FP Multipliers Common data bus (CDB) EE 524/Cpt. S 561 Advanced Computer Architecture

Cycle: 57 6 Load buffers From instruction unit FP operation queue From memory 5 4 3 2 1 FP Registers DIVD F 10, F 6 F 10: F 10 mult 2 M()*F 4 / M() Store buffers Operand buses 3 2 1 Operation bus 3 Reservation 2 To memory D M()*F 4 M[R 3] 1 Stations 1 FP adders 2 FP Multipliers Common data bus (CDB) Mult 2: M()*F 4 / M() EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 1 Yes EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 2 Note: Unlike 6600, can have multiple loads outstanding EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 3 • Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued vs. scoreboard • Load 1 completing; what is waiting for Load 1? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 4 • Load 2 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 5 EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 6 • Issue ADDD here vs. scoreboard? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 7 • Add 1 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 8 EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 9 EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 10 • Add 2 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 11 • Write result of ADDD here vs. scoreboard? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 12 • Note: all quick instructions complete already EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 13 EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 14 EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 15 • Mult 1 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 16 • Note: Just waiting for divide EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 55 EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 56 • Mult 2 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Example Cycle 57 • Again, in-order issue, out-of-order execution, completion EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Drawbacks • Complexity – delays of 360/91, MIPS 10000, IBM 620? • Many associative stores (CDB) at high speed • Performance limited by Common Data Bus – Multiple CDBs => more FU logic for parallel assoc stores EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Loop Example Loop: LD MULTD SD SUBI BNEZ F 0 F 4 R 1 0 F 0 0 R 1 Loop R 1 F 2 R 1 #8 • Assume Multiply takes 4 clocks • Assume first load takes 8 clocks (cache miss? ), second load takes 4 clocks (hit) • To be clear, will show clocks for SUBI, BNEZ • Reality, integer instructions ahead EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 0 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 1 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 2 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 3 • Note: MULT 1 has no registers names in RS EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 4 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 5 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 6 • Note: F 0 never sees Load 1 result EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 7 • Note: MULT 2 has no registers names in RS EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 8 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 9 • Load 1 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 10 • Load 2 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 11 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 12 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 13 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 14 • Mult 1 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 15 • Mult 2 completing; what is waiting for it? EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 16 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 17 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 18 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 19 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 20 EE 524/Cpt. S 561 Advanced Computer Architecture

Loop Example Cycle 21 EE 524/Cpt. S 561 Advanced Computer Architecture

Tomasulo Summary • Reservations stations: renaming to larger set of registers + buffering source operands – Prevents registers as bottleneck – Avoids WAR, WAW hazards of Scoreboard – Allows loop unrolling in HW • Not limited to basic blocks (integer units gets ahead, beyond branches) • Helps cache misses as well • Lasting Contributions – Dynamic scheduling – Register renaming – Load/store disambiguation • 360/91 descendants are Pentium II; Power. PC 604; MIPS R 10000; HP-PA 8000; Alpha 21264 EE 524/Cpt. S 561 Advanced Computer Architecture

Branch correction Fetch Unit Reorder buffer information Dispatch unit w/ 8 -entry instruction queue Instruction Cache Completion unit w/ reorder buffer Instruction dispatch buses Register nos. GP operand buses Instruction Operation buses Register nos. FP operand buses Reservation Stations XSU 0 XSU 1 MCFXU LSU GP result buses FPU BPU FP result buses Result status buses Data Cache EE 524/Cpt. S 561 Advanced Computer Architecture