Dynamic Random Access Memory DRAM Basic YenHao Chen
Dynamic Random Access Memory (DRAM) Basic Yen-Hao Chen yhchen@cs. nthu. edu. tw
DRAM Cell Arrays (Mats) • Accessing DRAM cell array data, include address and command decoding, bit line sensing, data I/O transport Row decoder Command, address transport 1. In bank data movement 2. System data transport Sense amplifier Address I/O gating I/O bus Read data latch Write drivers Columndecoder Column 2/34
Command Activate The Operation of DRAM Read Precharge Activate Data IO bus Bit line voltage Turn on the transistor The charge in the capacitor drives the bit line voltage The sense amplifier differentiate the voltage to VCC or VSS Bit lines are fully charged or discharged over time to store the latched data back into the cells in the open row Turn off the transistor Precharge the bit lines to (VCC+VSS)/2 Word line Transistor Capacitor 3/34
Timing Parameters Command Precharge Read Activate Data IO bus t. Burst t. RAS t. RP t. RCD t. AC t. CAS t. RAS: row access strobe t. RP: row precharge t. RC: row cycle (t. RAS + t. RP) t. RCD: row to column command delay t. CAS: column access strobe latency (t. CL), (t. AA) t. Burst: data burst duration (t. B) t. AC: access time (t. RCD + t. AA) 4/34
- Slides: 4