Dynamic Logic Introduction Dynamic CMOS l In static

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Dynamic Logic Introduction

Dynamic Logic Introduction

Dynamic CMOS l In static circuits at every point in time (except when switching)

Dynamic CMOS l In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. l l fan-in of n requires 2 n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. l requires on n + 2 (n+1 N-type + 1 P-type) transistors

Dynamic Gate Clk Mp off Mp on Out In 1 In 2 In 3

Dynamic Gate Clk Mp off Mp on Out In 1 In 2 In 3 Clk CL PDN A C B Me Clk Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) 1 Out ((AB)+C) off Me on

Conditions on Output l l l Once the output of a dynamic gate is

Conditions on Output l l l Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

Properties of Dynamic Gates l Logic function is implemented by the PDN only l

Properties of Dynamic Gates l Logic function is implemented by the PDN only l l number of transistors is N + 2 (versus 2 N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds l l l reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL

Properties of Dynamic Gates l Overall power dissipation usually higher than static CMOS l

Properties of Dynamic Gates l Overall power dissipation usually higher than static CMOS l l l PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn l l no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk low noise margin (NML) Needs a precharge/evaluate clock

Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk

Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk Me Evaluate VOut Precharge Leakage sources Dominant component is subthreshold current

Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me

Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic

Issues in Dynamic Design 2: Charge Sharing Clk Mp Out A CL B=0 Clk

Issues in Dynamic Design 2: Charge Sharing Clk Mp Out A CL B=0 Clk CA Me CB Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

Charge Sharing VDD Clk Mp Out CL A Ma X B=0 Clk Mb Me

Charge Sharing VDD Clk Mp Out CL A Ma X B=0 Clk Mb Me Ca Cb

Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge

Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

Issues in Dynamic Design 3: Backgate Coupling Clk Mp A=0 Out 1 =1 CL

Issues in Dynamic Design 3: Backgate Coupling Clk Mp A=0 Out 1 =1 CL 1 Out 2 =0 CL 2 B=0 Clk Me Dynamic NAND Static NAND In

Voltage Backgate Coupling Effect Out 1 Clk In Out 2 Time, ns

Voltage Backgate Coupling Effect Out 1 Clk In Out 2 Time, ns

Issues in Dynamic Design 4: Clock Feedthrough Clk Mp A CL B Clk Out

Issues in Dynamic Design 4: Clock Feedthrough Clk Mp A CL B Clk Out Me Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

Clock Feedthrough Clock feedthrough Clk Out In 1 In 3 In 4 Voltage In

Clock Feedthrough Clock feedthrough Clk Out In 1 In 3 In 4 Voltage In 2 In & Clk Out Clk Time, ns Clock feedthrough

Cascading Dynamic Gates V Clk Mp Out 1 Me Clk Out 2 In In

Cascading Dynamic Gates V Clk Mp Out 1 Me Clk Out 2 In In Clk Me Out 1 VTn V Out 2 t Only 0 1 transitions allowed at inputs!

Domino Logic Clk In 1 In 2 In 3 Clk Mp 1 1 1

Domino Logic Clk In 1 In 2 In 3 Clk Mp 1 1 1 0 PDN Me Out 1 Clk 0 0 0 1 In 4 In 5 Clk Mp Mkp PDN Me Out 2

Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Like falling dominos! Ini

Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Like falling dominos! Ini Inj PDN

Properties of Domino Logic l l Only non-inverting logic can be implemented Very high

Properties of Domino Logic l l Only non-inverting logic can be implemented Very high speed l l static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort

Designing with Domino Logic VDD VDD Clk Mp Clk Out 1 Mp Mr Out

Designing with Domino Logic VDD VDD Clk Mp Clk Out 1 Mp Mr Out 2 In 1 In 2 In 3 PDN In 4 Can be eliminated! Clk Me Clk Inputs = 0 during precharge Me

Footless Domino The first gate in the chain needs a foot switch Precharge is

Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage

Differential (Dual Rail) Domino off Mp Mkp Clk Out = AB 1 on Mkp

Differential (Dual Rail) Domino off Mp Mkp Clk Out = AB 1 on Mkp 0 Clk Mp 1 A !A 0 !B B Clk Me Solves the problem of non-inverting logic Out = AB

np-CMOS Clk In 1 In 2 In 3 Clk Mp 1 1 1 0

np-CMOS Clk In 1 In 2 In 3 Clk Mp 1 1 1 0 PDN Me Out 1 Clk Me In 4 In 5 PUN 0 0 0 1 Clk Mp Out 2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

NORA Logic Clk In 1 In 2 In 3 Clk Mp 1 1 1

NORA Logic Clk In 1 In 2 In 3 Clk Mp 1 1 1 0 Out 1 PDN Clk Me In 4 In 5 PUN 0 0 0 1 Clk Me to other PDN’s WARNING: Very sensitive to noise! Mp Out 2 (to PDN) to other PUN’s

Outline Introduction CMOS devices CMOS technology CMOS logicOutline Introduction CMOS devices CMOS technology CMOS logic
Lecture 07 Static CMOS Logic CMOS Circuit StylesLecture 07 Static CMOS Logic CMOS Circuit Styles
UNIT V CMOS LOGIC CMOS logic levels MOSUNIT V CMOS LOGIC CMOS logic levels MOS
Clockless Logic Review Logic Implementation Styles Static CMOSClockless Logic Review Logic Implementation Styles Static CMOS
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Introduction to CMOS Logic Circuits CMOS stands forIntroduction to CMOS Logic Circuits CMOS stands for
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5 CMOS Logic Basics1combinational logic Contents 1 Dynamic5 CMOS Logic Basics1combinational logic Contents 1 Dynamic
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Logic Introduction to Logic What is logic LogicLogic Introduction to Logic What is logic Logic
Digital CMOS Logic Circuits CMOS digital circuits smallDigital CMOS Logic Circuits CMOS digital circuits small
CMOS technology and CMOS Logic gate Transistors inCMOS technology and CMOS Logic gate Transistors in
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Dynamic Logic Circuits Static logic circuits allow implementationDynamic Logic Circuits Static logic circuits allow implementation
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Logic and Logic Programming Logic Propositional Logic FirstLogic and Logic Programming Logic Propositional Logic First