Dynamic Compilation Vijay Janapa Reddi The University of

Dynamic Compilation Vijay Janapa Reddi The University of Texas at Austin Interpretation

Our Objectives v v Discuss homework Understanding the basic nature of dynamic compilation. . . » The two forms of emulation, starting with interpretation -1 -

Why Bother with Dynamic Compilers? v v Modern computers are extremely complex Interfaces » ISA » OS interface (system calls) » API v Different interfaces for the same level » Different ISAs (Intel x 86, ARM, etc. . . ) » Different OSs (Linux, Windows, etc. . . ) -2 -

What Does It Mean to Compilation? v Problems? » Portability issue: (N OS ⇥M machine types) – solutions? » Interoperability issue: Hard to link language Xi with Xj -3 -

Introducing a New Flavor of Compilation v v Advantages/Disadvantages? Characteristics of source language/intermediate code? -4 -

Two Examples -5 -

Java Bytecode v v Nothing but an abstract machine description. . . Components » Instruction set Ÿ Characteristics u u u Platform independent “Write once, run anywhere” (WORA) “write once, run everywhere” (WORE) » Execution model Ÿ Characteristics u u Easy to emulate Enough complex to keep source language features » Metadata Ÿ Characteristics u High level description of “data” – Why? e. g. objects, structures -6 -

Java Bytecode v v v Source code to bytecode Bytecode to abstract virtual machine description VM to native code (and vice versa) » Bytecode verifier » Interpreter/JIT compiler » Memory management » Native APIs -7 -

Just-in-Time Compilation source v javac bytecode javac the Java bytecode compiler bytecode java execute v java the Java virtual machine v Bytecode: machine independent, portable Step One: “Compile” Circle. java % javac Circle. java -> Circle. class Step Two: “Execute” % java Circle. class -8 -

Bytecodes v v Each frame contains local variables and an operand stack Instruction set » » » v Load/store between locals and operand stack Arithmetic on operand stack Object creation and method invocation Array/field accesses Control transfers and exceptions The type of the operand stack at each program point is known at compile time -9 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v Computes: c : = 2 * (a + b) - 10 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v a 42 b 7 c 0 Computes: c : = 2 * (a + b) - 11 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v a 42 b 7 c 0 2 Computes: c : = 2 * (a + b) - 12 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v a 42 b 7 c 0 42 2 Computes: c : = 2 * (a + b) - 13 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v a 42 b 7 c 0 7 42 2 Computes: c : = 2 * (a + b) - 14 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v a 42 b 7 c 0 49 2 Computes: c : = 2 * (a + b) - 15 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v a 42 b 7 c 0 98 Computes: c : = 2 * (a + b) - 16 -

Bytecodes (cont. ) v Example: iconst 2 iload a iload b iadd imul istore c v a 42 b 7 c 98 Computes: c : = 2 * (a + b) - 17 -

Stack vs. Register-Based Code v Stack-based v » Operands are expressed implicitly Register-based » Operands are expressed explicitly » Less pushing/popping » Larger code » More optimization - 18 -

Java VM versus Dalvik VM v v - 19 - �Java is purely stack based Dalvik is register based

Executing Bytecode v java Circle. class - What happens? v Interpreting » map each bytecode to a machine code sequence, » for each bytecode, execute the sequence v Translation to machine code » map all the bytecodes to machine code (or a higher level intermediate representation) » massage them (e. g. , remove redundancies) » execute the machine code - 20 -

What is an Interpreter? Source Code Program Inputs Interpreter - 21 - Program Outputs

What is a Just-in-Time Compiler? Source Code IR Generator Intermediate Program Inputs Virtual Machine - 22 - Program Outputs

Emulation Vs. Simulation v Emulation » Method for enabling a (sub)system to present the same interface and characteristics as another » Ways of implementing emulation Ÿ Interpretation: relatively inefficient instruction-at-a-time Ÿ Binary Translation: Block-at-a-time optimized for repeated » Eg: The execution of programs compiled for instruction set A on a machine that executes instruction set B v Simulation » Method for modeling a (sub)system’s operation. » Objective is to study the process; not just to imitate the function » Typically emulation is part of the simulation process. - 23 -

Definitions v Guest » Environment being supported by underlying platform v Host » Underlying platform that provides guest environment v How do I know what to do? ! » http: //docs. oracle. com/javas e/specs/jvms/se 7/html/jvms -4. html#jvms-4. 10 - 24 - Guest supported by Host

Definitions (2) v Source ISA or binary » Original instruction set or binary » The ISA to be emulated v Target ISA or binary » ISA of the host processor Source emulated by » Underlying ISA v Source/Target refer to ISAs v Guest/Host refer to platforms - 25 - Target

Emulation v v Required for implementing many VMs Process of implementing the interface and functionality of one (sub)system on a (sub)system having a different interface and functionality » Terminal emulators, such as VT 100, xterm, putty v Instruction set emulation » Binaries in source instruction set can be executed on machine implementing target instruction set » Eg: IA-32 execution layer - 26 -

Interpretation versus Translation v Interpretation » Simple and easy to implement, portable » Low performance » Threaded interpretation v Binary Translation » Complex implementation » High initial translation cost, small execution cost. » Selective compilation v We focus on user-level instruction set emulation of program binaries. - 27 -

Interpreter State v An interpreter needs to maintain the complete architected state of the machine implementing the source ISA » Registers » Memory Program Counter Condition Codes Code Reg 0 Reg 1. . . Data Reg n-1 Ÿ Code Ÿ Data Ÿ stack Stack - 28 - Interpreter Code

Decode-Dispatch Interpreter v Decode and dispatch interpreter » » step through the program one instruction at a time decode the current instruction dispatch to corresponding interpreter routine very high interpretation cost while (!halt && !interrupt) { inst = code[PC]; opcode = extract(inst, 31, 6); switch(opcode) { case Load. Word. And. Zero: Load. Word. And. Zero(inst); case ALU: ALU(inst); case Branch: Branch(inst); … } } - 29 -

Decode-Dispatch Interpreter (2) v Instruction Function: Power. PC Load (LWZ) Load. Word. And. Zero (inst) { RT = extract(inst, 25, 5); RA = extract(inst, 20, 5); displacement = extract(inst, 15, 16); if (RA == 0) source = 0; else source = regs[RA]; address = source + displacement; regs[RT] = (data[address]<< 32)>> 32; PC = PC + 4; } - 30 -

Decode-Dispatch Interpreter (2) v Instruction Function: Power. PC Load (LWZ) Load. Word. And. Zero (inst) { RT = extract(inst, 25, 5); RA = extract(inst, 20, 5); displacement = extract(inst, 15, 16); if (RA == 0) source = 0; else source = regs[RA]; address = source + displacement; regs[RT] = (data[address]<< 32)>> 32; PC = PC + 4; } - 31 -

Decode-Dispatch Interpreter (3) v Instruction Function: ALU (inst) { RT = extract(inst, 25, 5); RA = extract(inst, 20, 5); RB = extract(inst, 15, 5); source 1 = regs[RA]; source 2 = regs[RB]; extended_opcode = extract(inst, 10); switch(extended_opcode) { case Add: Add(inst); case Add. Carrying: Add. Carrying(inst); case Add. Extended: Add. Extended(inst); . . . } PC = PC + 4; } - 32 -

Interpreter Behavior 1. 2. 3. 4. 5. 6. - 33 - Fetch the opcode Go to the right “switch case” Call the right routine Emulate the bytecode Return to the caller Restart

Decode – Dispatch Efficiency v Decode-Dispatch Loop » » v mostly serial code case statement call to function routine return Executing an add instruction » approximately 20 target instructions » several loads/stores and shift/mask steps v Hand-coding can lead to better performance » Eg: DEC/Compaq FX!32 - 34 -