DWT Horizontal lev 1 Vertical lev 1 Horizontal
- Slides: 39
提案2次元DWTアルゴリズム 従来方式 Horizontal lev. 1 Vertical lev. 1 Horizontal lev. 2 Vertical lev. 2 提案方式 Horizontal lev. 1 Horizontal lev. 2 Vertical lev. 1 Vertical lev. 2
転置メモリ容量の比較 512× 512ピクセル画像 (5, 3) フィルター 従来 Overlapped Linebased block 提案 メモリー (ワード数) 262, 144 2, 555 4, 096 32, 768 種別 memory register memory
部分ゼロツリーEZW探索 PS Vertical DWT coefs IZ NS IZ ZR - IZ ZR ZR Input to vertical DWT - ZR ZR PS Horizontal lev. 3 (Low-freq. ) ZR - ZR IZ - IZ PS Partial zerotree
システム全体のメモリ容量の比較 512× 512ピクセル画像 (5, 3) フィルター 従来 Overlapped Linebased block 提案 DWT 262, 144 2, 555 4, 096 32, 768 EZW 262, 144 32, 768 合計 524, 188 264, 699 266, 240 65, 536
復元画像 Football frame # 10 MPEG-2 (PSNR: 28. 2 d. B) DWT (PSNR: 30. 2 d. B)
提案符号化器の全体構成 Pixel data M U X Horizontal lev. 3 L DWT Unit Stage 1 FU Stage 2 FU M U X AC Unit EZW Unit Compressed dominant code Output Buffer Horizontal lev. 3 L Line Buffer Control Horizontal Partial zerotrees Dominant Path code Line Buffer DMA External SDRAM
EZWユニット bitplane 1(MSB) 0 Compare +00110 ビットストリーム bitplane 2 bitplane 3 0 +1(MSB) bitplane 4 bitplane 5(LSB) 1 +001 Update Sub. Bits Gen. 10 Dominant Path Code Subordinate Path Code メモリアクセス回数の削減: 全てのビットを並列に処理 0
AC (arithmetic coder) ユニット bitplane i symbol (PS/NS/ZR/IZ) bitplane i-1 symbol state transition table current state bitplane i+1 symbol (PS/NS/ZR/IZ) bitplane i output code new state register bitplane i symbol state transition table bitplane i +1 output code new state current state register 全てのビットプレーンの処理を並列に行う
水平モードにおける動作 M Pixel U Data X DWT Unit Stage 1 FU Stage 2 FU M U X Horizontal lev. 3 L Line Buffer Control Line Buffer Dominant Path code AC Unit EZW Unit Compressed dominant code Output Buffer Horizontal Partial zerotrees DMA External SDRAM
垂直モードにおける動作 M U X Horizontal lev. 3 L Dominant Path code DWT Unit Stage 1 FU Stage 2 FU M U X AC Unit EZW Unit Compressed dominant code Output Buffer Horizontal Partial zerotrees Line Buffer Control Line Buffer DMA External SDRAM
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