DPPM for Analog and RF Circuits Vishwani D

DPPM for Analog and RF Circuits Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA vagrawal@eng. auburn. edu Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA szs 0063@auburn. edu 32 nd IEEE VLSI Test Symposium Napa, California April 14, 2014

Problem Statement • Given: – A set of complete specification-based tests for an analog or RF circuit, and – An acceptable defect level (DL), • Find the smallest set of tests that should be used. 3/13/2014 LATW 2014: Spec. Test Minimization 2

A Bipartite Graph Tests T 1 p 11 S 1 T 2 p 12 p 21 p 22 S 2 T 3 p 13 p 33 S 3 T 4 p 42 p 34 p 44 S 4 Specifications 3/13/2014 LATW 2014: Spec. Test Minimization 3

Operational Amplifier: TI LM 741 3/13/2014 LATW 2014: Spec. Test Minimization 4

Test Minimization DL PPM x 1 0 1 100 1 1, 000 0 10, 000 0 3/13/2014 x 2 1 1 1 ILP solution x 3 x 4 x 5 1 1 0 1 0 0 1 x 6 1 1 1 x 7 1 1 1 LATW 2014: Spec. Test Minimization Tests Test size selected reduction 7 6 6 5 4 0% 14% 29% 43% 5

Conclusion • Specification tests are given. • Monte Carlo spice simulation determines probability, pij, of ith test checking for jth specification. • An integer linear program (ILP) determines the defect level for any number of tests. • References: – S. Sindia and V. D. Agrawal, “Specification Test Minimization for Given Defect Level, ” Proc. 15 th IEEE Latin -American Test Workshop, Fortaleza, Brazil, March 13, 2014. – A detailed paper submitted to ITC 2014. 3/13/2014 LATW 2014: Spec. Test Minimization 6