Double Data Rate SDRAM The Next Generation An

Double Data Rate SDRAM – The Next Generation An overview of the industry roadmap for main system memory technology, and details on DDR which represents the latest state of the art for SDRAM. We will cover: • The industry standards process for product definition • The evolution of main memories • Comparing DDR to SDRAM • DDR configuration options & applications • Design tricks for DDR systems • What’s next for main memory?

The JEDEC Standards Process

The JEDEC Standards Process • JEDEC is a non-profit standards organization • 265 member companies from all over the world • Suppliers & users and even competitors • Working together to expand the market

How standards get done • • • Any company presents a market need Interested companies form a Task Group TG does development, submits ballot to committee Feedback from voting incorporated into spec The new standard is published Task Group reforms as needed for enhancements

Industry Evolution from SDRAM to DDR

Main Memory DRAM Evolution Mainstream Memories 4800 MB/s 2100 MB/s 1000 MB/s M A 400 MB/s R D S 320 MB/s EDO FP R D D II Simple, incremental steps

Cost remains constant • The top three factors driving memory evolution 1. Cost 2. Cost 3. Cost • • • The price of memory has remained essentially constant Each incremental enhancement must “come for free” “Free” means similar evolution of costs: – Direct: die size, packaging, testers, licensing – Indirect: PCB complexity, heat sinks, support components – 2 x indirect: dummy continuity boards

What is DDR? • Internally, DDR is an SDRAM with ping pong registers • Data is posted on rising and falling edges of the clock • Commands still sampled on rising edge

How Different is DDR? • Simple upgrade from SDRAM designs –Same PCB characteristics: 60 6 –Same RAS/CAS command set • A few evolutionary improvements –Low voltage swing I/O –Differential clocks –Source synchronous data strobe

DDR low voltage signaling DDR • SSTL_2 low voltage swing inputs – 2. 5 V I/O with 1. 25 V reference voltage –Low voltage swing with termination –Rail to rail if unterminated

DDR Differential Clocks • Route differential clocks on adjacent traces • Timing is relative to crosspoint • Helps insure 50% duty cycle

DDR Read Timing – Data delivered on both edges of CK • Data valid on rising & falling edges • Data Strobe “DQS” travels with data • DLL aligns data to clock edges

Emphasis on “Matched” CONTROLLER DDR SDRAM DQ/DQS VREF DM VREF Disable • DM/DQS loading identical to DQ • Route as independent 8 bit buses

Combining 8 bit buses into internal bus width DQ 8 DQS DM DQ DQS DM 8 Clocked in memory time domain Clocked in controller time domain Internal Memory FIFO • Each byte samples using DQS as input strobe • Input buffers capture one odd and one even byte • Commit to FIFO on controller clock DQ 8 DQS DM

DDR Configuration Options for Different Applications

DDR Configurations TSOP SO-DIMM TQFP

DDR Configurations, Chips Ü 66 pin TSOP-II –Inexpensive high volume plastic package –Compatible pinout for X 4, X 8, X 16 – 64 Mb to 512 Mb; 1 Gb in development Ü 100 pin TQFP –Inexpensive high volume plastic package –X 32 configuration – 64 Mb and 128 Mb

DDR Configurations, Modules Ü Desktop & Server 184 pins, 5. 25” long X 64 or X 72 (ECC) 64 MB to 2 GB Mobile & Small Form Factor Þ 200 pins, 2. 7” long X 64 or X 72 (ECC) 32 MB to 512 MB

DDR Unbuffered DIMM DDR SDRAM Data • • DDR SDRAM Address Least expensive module Limits number of loads supportable Address bus hits all DDR SDRAMs Fastest access time Data DDR SDRAM Data

DDR Registered DIMM DDR SDRAM Register Data • • • Address Data Doubles density of each module or halves number of address buses needed Address bus latched before going to DDR SDRAMs Access time increased by one clock

DDR Tips and Tricks for Power Management

Closed Page Open Page Power Management Power State* Active on Relative Power 100% CPU Clocks of Latency** 0*5=0 Inactive on 12% 3 * 5 = 15 Active off 4% 1*5=5 Inactive off 0. 2% 4 * 5 = 20 Sleep 0. 4% 200*5 = 1000 * Not industry standard terms – simplified for brevity **Assumes 5 CPU clocks per memory clock

Power: DDR vs SDRAM DDR-266 3 X DDR-333 2. 6 X (est) PC-100 1 X PC-133 0. 8 X

What’s next for DDR?

Next: Enhancing DDR from 266 to 333 MHz data rate • • Qualification of DDR 333 under way Possibly different DDR SDRAM packages for each solution: – – Unbuffered DIMM: FBGA Registered DIMM: TSOP SO-DIMM: TSOP Point to point: TSOP

Next: Small Packages FBGA • Lower inductance • Lower capacitance • Smaller footprint • Tighter layouts enabled Details: Package size = 104 mm 2 = 54% smaller Inductance: 1. 7 n. H lower Inductance variation, pin to pin: 3 X less Capacitance: 0. 5 p. F lower Performance gain: 300 ps of data valid time

Next: DDR FET Switched DIMM DDR SDRAM FET Data • • DDR SDRAM Register Address DDR SDRAM FET Data Quadruples density of each module or doubles number of DIMM slots Address bus latched before going to DDR SDRAMs Data bus sees a single load per slot Additional bus turnaround latency

Next: DDR Micro. DIMM • Half the size of the DDR SO-DIMM • Half the capacity if using TSOP – or – • Same capacity if using FBGA • Target markets: –PDAs –Internet appliances –Subnotebook computers

Next: DDR II • Work well under way on DDR II • Double the speed • Lower power • Migration path from DDR I –Same controller can use DDR I and DDR II –Compatible process technologies

Conclusions • DDR is a result of collaboration between many companies • Cost drives incremental evolutionary steps • DDR is a simple evolution of SDRAM technology • Configuration options available for different applications • Use tricks and techniques to exploit DDR’s features • The future of DDR is in evolutionary steps