Dominance Fault Collapsing of Combinational Circuits By Kalpesh

Dominance Fault Collapsing of Combinational Circuits By Kalpesh Shetye & Kapil Gore ELEC 7250, Spring 2004

Introduction A program is written in MATLAB for dominance fault collapsing of combinational circuits. The resulting collapsed fault set is compared with the equivalence collapsed fault set obtained from HITEC ATPG software. Input Files . bench &. name Output File . eqf The program also counts the number of collapsed faults and displays the time taken for computation. Program is compatible with XOR & XNOR gates.

INPUT 1 INPUT 2 INPUT 3 INPUT 6 INPUT 7 OUTPUT 22 OUTPUT 23 NAND 1 3 10 NAND 3 6 11 NAND 2 11 16 NAND 11 7 19 NAND 10 16 22 NAND 16 19 23 . bench file

Analysis The program uses structural dominance fault collapsing. The rules used are as follows: 1. To collapse faults of a gate, all faults from the output can be eliminated retaining one type of fault on each input of the gate and the other type on any one of the inputs. 2. The output faults of the NOT gate, the non-inverting buffer and the wire can be removed as long as both faults on the input are retained. 3. No collapsing is possible for fan-outs. 4. No collapsing is possible for XOR and XNOR gates.

Algorithm The algorithm used is as follows: 1. 2. 3. 4. Assign tokens to all gates. Construct input, output and gate array. Construct fanout array. Identify input fanout nodes and assign s-a-0 and s-a-1 faults.

5. 6. 7. 8. Consider the first gate and check if any of its inputs is the output of another gate. If yes, then set flag bit. Check the inputs of the same gate with the fanout array and check its flag bit. If flag bit is set and a match is found, assign one stuck-at fault at that input. If flag bit is not set and a match is found, then assign two stuck-at faults and set flag bit. Repeat the above step for comparison with the input array instead of the fanout array. Repeat steps 5 to 7 for all the remaining gates.

Results Circuit Under Test MATLAB program HITEC 1 c 17 bench file Collapsed faults = 16 Detected faults = 16 Redundant faults = 0 Fault Coverage = 100% Collapsed faults = 22 Detected faults = 22 Redundant faults = 0 Fault Coverage = 100% 2 74181 bench file (with XOR) Collapsed faults = 192 No provision for XOR and XNOR gates 3 74181 bench file (with each XOR replaced by 4 NAND gates) Collapsed faults = 232 Detected faults = 224 Redundant faults = 8 Fault Coverage = 96. 55% Collapsed faults = 301 Detected faults = 293 Redundant faults = 8 Fault Coverage = 97. 34%

Conclusion On the basis of the results, we make the following conclusions: 1. For small circuits, both dominance as well as equivalence fault collapsing result in identical fault coverage. 2. For large circuits, equivalence fault collapsing results in larger fault coverage than dominance fault collapsing. 3. Size of collapsed fault set obtained by dominance is smaller than that obtained by equivalence. 4. For large circuits, selection of either technique for fault collapsing is essentially a trade-off between time taken for testing and fault coverage.

Suggested Improvements Incorporate test vector generation routine and fault simulation routine. References [1] HITEC/PROOFS User’s manual. [2] Essentials of Electronic Testing for Digital Memory and Mixed. Signal VLSI Circuits, Michael Bushnell and Vishwani Agrawal.

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