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doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Project: IEEE

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Project: IEEE P 802. 15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [Comparison of IEEE 802. 15. 4 b High Rate Alt-PHY proposals] Date Submitted: [13 Sept, 2004] Source: [Francois Chin] Company: [Institute for Infocomm Research, Singapore] Address: [21 Heng Mui Keng Terrace, Singapore 119613] Voice: [65 -68745684] FAX: [65 -67768109] E-Mail: [chinfrancois@i 2 r. a-star. edu. sg] Re: [Response to the call for proposal of IEEE 802. 15. 4 b, Doc Number: 15 -04 -0239 -00 -004 b] Abstract: [This presentation compares all proposals for the IEEE 802. 15. 4 b PHY standard. ] Purpose: [Proposal to IEEE 802. 15. 4 b Task Group] Notice: This document has been prepared to assist the IEEE P 802. 15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P 802. 15. Submission 1 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Summary of

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Summary of Proposed Code Sets Code Set A 32 B 16 C 8 D 8 E 16 F 31 G 16 Description 32 -chip (15. 4 original) 16 -chip 8 -chip for Coh. Chip Despreading 8 -chip for Diff. Chip Despreadin g Orthogonal 16 -DSSS PSSS 8 -chip for Coh. Chip Despreadin g Proposer Motorola / Freescale I 2 R Helicomm Dr. Wolf & Assoc. I 2 R Doc # 04 -189 04 -403 04 -507(new) 04 -403 04 -314 04 -121 04 -507(new) Sym-Chip mapping Cyclic & Odd Bit Inversion (COBI) Cyclic & Odd Bit Inversion Orthogonal Multi-code Cyclic & Odd Bit Inversion Bit/sym 4 4 4 3 4 15 4 Chip/Sym 32 16 8 8 16 31+1 cyclic extension 16+1 cyclic extension Bit/chip 0. 125 0. 375 0. 25 ~0. 47 ~0. 24 Root Sequence D 9 C 3522 E 3 AFC 5 C 45 N. A. 08 B 3 E 375 2 F 53 Coh. Chip Despreading (CCD) Yes Yes Differential Chip Despreading (DCD) Yes No No No Submission 2 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 BER Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 BER Performance Comparison Code Sequence A 32 D 8 B 16 C 8 E 16 Performance of proposed 16 -chip and 8 -chip code sets, in comparison with original 802. 15. 4 PHY length-32 Symbol-to-Chip performance and Orthogonal DSSS sequences as in 15 -04 -0314 -00 -004 b -enhanced-oqpsk-modulation-with-orthogonal-dsss-sequences Submission 3 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Comparison Methodology

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Comparison Methodology – – Multipath robustness performance Bandwidth efficiency (bps / Hz) RF requirement Memory requirement Submission 4 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Realisations

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Realisations 100 Channel Realisations at each RMS Delay Spread Submission 5 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Realisations

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Realisations 100 Channel Realisations at each RMS Delay Spread Submission 6 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Candidates for

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code Set A 32 B 16 D 8 Description 32 -chip (15. 4 original) 16 -chip 8 -chip for Diff. Chip Despreading Proposer Motorola / Freescale I 2 R Doc # 04 -189 04 -403 Sym-Chip mapping Cyclic & Odd Bit Inversion (COBI) Cyclic & Odd Bit Inversion Bit/sym 4 4 3 Chip/Sym 32 16 8 Bit/chip 0. 125 0. 375 Root Sequence D 9 C 3522 E 3 AFC 45 Coh. Chip Despreading (CCD) Yes Yes Differential Chip Despreading (DCD) Yes Yes Submission 7 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Proposed Symbol-to-Chip

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Proposed Symbol-to-Chip Mapping (16 -chip Code Set B 16) Decimal Value Binary Symbol Chip Value 0 0000 1 1000 0000111010111111 2 0100 1100001110101111 3 1100 1111000011101011 4 0010 1111110000111010 5 1010 1011111100001110 6 0110 1010111111000011 7 1110101111110000 8 0001 0110111110101001 9 1001 0101101111101010 10 0101 1001011011111010 11 1101 1010010110111110 12 0011 1010100101101111 13 1011 1110101001011011 14 0111 1111101010010110 0 0 1 1 1 0 0 (Root 3 AFC) 15 1111 1011111010100101 The sequences are related to each other through cyclic shifts and/or conjugation (i. e. , inversion of odd-indexed chip values) 8 Submission Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root Sequences (16 -chip Code Set B 16) • The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 141 1205 2436 4820 5581 7568 9542 11585 13246 15440 16685 17957 19745 20960 22369 24558 26347 28585 29977 32440 Submission 177 282 311 354 473 537 564 609 708 965 1074 1127 1128 1218 1244 1310 1385 1416 1475 1565 1841 1892 2067 2148 2256 2405 2747 2832 3095 3201 3541 3775 3860 4107 4134 4211 4296 4508 4512 4872 4901 4976 5077 5135 5240 5273 5330 5411 5494 5497 5540 5587 5664 5749 5900 6260 6293 6402 6517 6593 6657 7082 7364 7430 7685 8110 8214 8259 8268 8525 8592 8879 8981 9024 9211 9491 9620 9744 9797 9982 10154 10988 10994 11162 11174 11245 11328 11498 11755 11939 12190 12279 12380 12417 12551 12626 12637 12804 12881 13034 13314 13399 13445 14011 14081 14164 14319 14987 15031 15100 15331 15357 15610 15697 15867 16015 16102 16306 16419 16428 16502 16518 16536 16625 16730 16775 16844 16985 17184 17269 17609 17653 17702 17758 17779 17821 18013 18032 18048 18305 18515 18629 18833 19195 19280 19488 19543 19604 19904 20223 20308 20540 20555 20630 20701 20786 20797 20839 20873 20887 21041 21092 21320 21559 21583 21602 21644 21976 21988 22160 22324 22348 22417 22656 22850 22996 23105 23530 23600 23761 23857 23878 23941 24133 24834 24919 25040 25089 25172 25274 25582 25607 25608 25682 25865 26068 26372 26449 26559 26628 26798 26885 27055 27367 27571 27610 28328 28342 28638 28642 28691 28742 28865 29439 29456 29509 29611 29720 29893 29974 30019 30229 30272 30382 30714 30740 30910 30997 31167 31394 31435 31734 32463 …. 9 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Proposed Symbol-to-Chip

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Proposed Symbol-to-Chip Mapping (8 -chip Code Set D 8) 3 -bit / symbol mapping Decimal Value Binary Symbol Chip Value 0 000 1 100 01010001 2 01010100 3 110 00010101 4 001 00010000 5 101 00000100 6 011 00000001 7 111 01000000 01000101 (root – 45 h) The sequences are related to each other through cyclic shifts and/or conjugation (i. e. , inversion of odd-indexed chip values) Submission 10 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root Sequences (8 -chip Code Set D 8) • The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 1 4 16 21 64 69 81 84 171 174 186 191 234 239 251 254 Submission 11 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 AWGN Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 AWGN Performance (Differential Chip Despreading) Performance comparison • 32 -chip ~ 8 -chip (3/8 bit/chip) > 16 -chip Submission 12 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance (Differential Chip Despreading) Performance - 32 -chip (1/8 bit/chip) > 16 -chip (1/4 bit/chip) > 8 -chip (3/8 bit/chip) Submission 13 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance (Differential Chip Despreading) @ 1 us RMS delay spread (RMS delay spread / chip period > 0. 3), no apparent BER floor Submission 14 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance (Differential Chip Despreading) @ 2 us RMS delay spread (RMS delay spread / chip period < 0. 6), apparent BER floor Submission 15 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance Summary (Differential Chip Despreading) • When RMS delay spread / chip period > 0. 3, inter–chip interference (ICI) sets in • Sequence length helps, but does not eliminate ICI …. • Coherent chip despreading is explored next …. Submission 16 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Candidates for

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code Set C 8 E 16 F 31 G 16 Description 8 -chip for Coh. Chip Despreading Orthogonal 16 DSSS PSSS 8 -chip for Coh. Chip Despreading Proposer I 2 R Helicomm Dr. Wolf & Assoc. I 2 R Doc # 04 -507 04 -314 04 -121 04 -507(new) Sym-Chip mapping Cyclic & Odd Bit Inversion Orthogonal Multi-code Cyclic & Odd Bit Inversion Bit/sym 4 4 15 4 Chip/Sym 8+1 cyclic extension 16+1 cyclic extension 31+1 cyclic extension 16+1 cyclic extension Bit/chip 0. 44 0. 25 ~0. 47 ~0. 24 Root Sequence 5 C N. A. 08 B 3 E 375 2 F 53 Coh. Chip Despreading (CCD) Yes Yes Differential Chip Despreading (DCD) No No Submission 17 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root Sequences (8 -chip C 8 for Coherent Despreading only) • The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 9 18 23 29 33 36 46 58 66 71 72 92 111 113 116 123 132 139 142 144 163 184 189 197 209 219 222 226 232 237 246 Submission 18 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 DSSS Sequence

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 DSSS Sequence E 16 Decimal Symbol Binary Symbol Chip Values 0 0000 001101000100 1 1000 011000010001 2 0100 000001110111 3 1100 010100100010 4 0010 0011101101001011 5 1010 0110111000011110 6 1110 00001111000 7 0111 0101110100101101 8 0001 001101001011 9 1001 011000011110 10 0101 000001111000 11 1101 010100101101 12 001110110100 13 1011 011011100001 14 0111 000010000111 15 1111 010111010010 Source doc. : IEEE 802. 15 -04 -0314 -02 -004 b Submission 19 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 PSSS Sequence

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 PSSS Sequence F 31 (15 bit/32 chip) Source doc. : IEEE 802. 15 -04 -0121 -04 -004 b No Pre-coding is employed in this simulation Submission 20 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Other Root Sequences (8 -chip G 16 for Coherent Despreading only) • The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: 1915 22715 44497 Submission 3566 31238 53420 12115 34297 61969 21 21038 42820 63620 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance (Coherent Chip Despreading) For DSSS, 2 RAKE fingers are required to over BER floor Submission 22 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance (Coherent Chip Despreading) For PSSS, 2 RAKE fingers are required to over BER floor Submission 23 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance (Coherent Chip Despreading) For 8 -chip COBI Sequence, 2 RAKE fingers are required to over BER floor Submission 24 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance (Coherent Chip Despreading) For 16 -chip COBI Sequence, 2 RAKE fingers are required to over BER floor Submission 25 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Coherent Receiver

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Coherent Receiver Multipath Performance Given receiver with 2 RAKE fingers • all Sequence gives 2 d. B ~ 6 d. B gain by using additional Cyclic-Prefix chip to achieve best performance / data rate trade off • PSSS (31+1 chip) > COBI sequence (8+1 chip) > COBI sequence (16+1 chip) > DSSS Sequence (16 +1 chip); all coding schemes are within 3 d. B from each other Submission 26 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Coherent Receiver

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Coherent Receiver Multipath Performance General performance comparison: • PSSS (31+1 chip) > COBI sequence (8+1 chip) > COBI sequence (16+1 chip) > DSSS Sequence (16 +1 chip) What leads to Multipath robustness? Frequency selectivity leads to Inter-chip interference, and that is the killer…. To overcome, code must have good autocorrelation properties, i. e. low sidelodes. Submission 27 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 How these

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 How these codes achieve Multipath robustness? • PSSS, uses flexibility in amplitude to achieve zero auto-correlation throughout • COBI, maintain constant module, can at best achieve zero auto-correlation within 2 chips from cor. Peak; that is good enough to handle ICI of upto 2 chip periods • DSSS, comprising Walsh sequences, has autocorrelation sidelodes Submission 28 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Multipath Performance Summary (Coherent Chip Despreading) • To combat inter-chip interference due to relatively large channel delay spread (RMS delay spread / chip period ~ 0. 6), 2 recommendations are: • RAKE combining (with 2 fingers) in receiver to combine path diversity; (this does not affect standard) • One additional chip extension to the chip sequence to avoid intersymbol interference (this one does) • With the 2 recommendations, • @ BER = 10 -5 (PER ~ 1% @ 127 byte-packet), all three candidates (namely, DSSS, PSSS (without pre-coding) and 8 -chip COBI Sequence) are working within 3 d. B difference, under large channel delay spread Submission 29 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Candidates for

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Candidates for Multipath Performance Comparison (using Coherent Chip Despreading) Code Set C 8 E 16 F 31 G 16 Description 8 -chip for Coh. Chip Despreading Orthogonal 16 DSSS PSSS 8 -chip for Coh. Chip Despreading Proposer I 2 R Helicomm Dr. Wolf & Assoc. I 2 R Doc # 04 -507 (new) 04 -314 04 -121 04 -507 (new) Sym-Chip mapping Cyclic & Odd Bit Inversion Orthogonal Multi-code Cyclic & Odd Bit Inversion Bit/sym 4 4 15 4 Chip/Sym 8+1 cyclic extension 16+1 cyclic extension 31+1 cyclic extension 16+1 cyclic extension Bit/chip 0. 44 0. 25 ~0. 47 ~0. 24 Multipath performance Robust Memory requirement Low High Moderate Low RF linearity requirement Low Moderate ~ high Low Note : Red - desirable Submission 30 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Code Sequence

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Code Sequence Recommendations • Multipath robustness vs complexity • Differential chip despreading can only support multipath channels with RMS delay spread around 1 us with chip rate 300 kcps (RMS delay spread-chip period ~ 0. 3, that means ~ 300 ns with half rate 1 Mcps, proposed in 915 MHz) • As multipath robustness is vital, and differential chip despreading does not perform well under channels with excessive delay spread, coherent chip despreading is needed to ensure coverage • 8 -chip & 16 -chip COBI sequence is recommended for its low RF linearity requirement, high bandwidth efficiency and low memory requirement Submission 31 Francois Chin, Institute for Infocomm Research (I 2 R)

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Recommendations for

doc. : IEEE 802. 15 -04 -0507 -00 -004 b Sept 2004 Recommendations for low GHz Bands Ch #0 868 MHz band Ch #1 -10 906 – 924 MHz band Bandwidth 600 k. Hz 2 MHz Recommend ed Code Set 8 -chip COBI C 8 (4/9 bit/chip) 16 -chip COBI G 16 (4/17 bit/chip)** Receiver Cohent Chip Despreading Chip rate 300 kcps 400 kcps 1 Mcps Pulse shape Half-sine Modulation OQPSK Data rate 133. 3 kbps 177. 8 kbps 444 kbps 235 kbps ** Code sequence & related multipath robustness performance available soon Submission 32 Francois Chin, Institute for Infocomm Research (I 2 R)